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DSC557-04331KE1-T Datasheet(PDF) 2 Page - Micrel Semiconductor

Part # DSC557-04331KE1-T
Description  Crystal-less??Three Output PCIe Clock Generator
Download  7 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

DSC557-04331KE1-T Datasheet(HTML) 2 Page - Micrel Semiconductor

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______________________________________________________________________________________________________________________________________________
DSC557-04
Page 2
DSC557-04
Crystal-less Three Output PCIe Clock Generator
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)
Notes:
1.
VDD should be filtered with 0.01uf capacitor.
2.
Output is enabled if OE pin is floated or not connected.
3.
tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
4.
Output Waveform and Connection Diagram define the parameters.
5.
Period Jitter includes crosstalk from adjacent output.
6.
Contact Sales@Discera.com for alternate output options (LVPECL, LVDS, LVCMOS).
7.
Contact Sales@Discera.com for alternative frequency options
8.
Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Voltage1
VDD
2.25
3.6
V
Supply Current
IDD
EN pin low – outputs are
disabled
42
46
mA
Supply Current2
(Two HCSL Outputs)
IDD
EN pin high – outputs are
enabled
RL=50 Ω, FO1=FO2=FO3=100 MHz
100
mA
Frequency Stability
Δf
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
±100
ppm
±50
Startup Time3
tSU
T=25°C
5
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
0.25xVDD
V
Output Disable Time4
tDA
5
ns
Output Enable Time
tEN
20
ns
Pull-Up Resistor2
Pull-up on OE pin
40
HCSL Outputs6
Parameter
Condition
Min.
Typ.
Max.
Unit
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
0.725
-
-
0.1
V
Pk to Pk Output Swing
Single-Ended
750
mV
Output Transition time4
Rise Time
Fall Time
tR
tF
20% to 80%
RL=50Ω, CL= 2pF
200
400
ps
Frequency
f0
Single Frequency
2.3
1007
460
MHz
Output Duty Cycle
SYM
Differential
48
52
%
Period Jitter5
JPER
FO1=FO2= FO3 =100 MHz
2.5
psRMS
Jitter, Phase
(Common Clock
Architecture)
TJ
PCIe Gen 1.1
22.7
86.08
psp-p
JRMS-CCHF
PCIe Gen 2.1, 1.5MHz to Nyquist
2.20
3.18
psRMS
JRMS-CCLF
PCIe Gen 2.1, 10 kHz to 1.5 MHz
0.08
3.08
psRMS
JRMS-CC
PCIe Gen 3.0
0.37
1.08
psRMS
Integrated Phase Noise
(Data Clock
Architecture)
JRMS-DCHF
PCIe Gen 2.1, 1.5MHz to Nyquist
2.15
4.08
psRMS
JRMS-DCLF
PCIe Gen 2.1, 10 kHz to 1.5 MHz
0.06
7.58
psRMS
JRMS-DC
PCIe Gen 3.0
0.32
1.08
psRMS


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