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OMAPL138BGWTMEP Datasheet(PDF) 4 Page - Texas Instruments |
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OMAPL138BGWTMEP Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 284 page  OMAPL138B-EP SPRS815C – DECEMBER 2011 – REVISED APRIL 2013 www.ti.com 1.3 Description The OMAPL138B C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K- byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance. For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects the users’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the TMS320C674x/OMAP-L1x Processor Security User’s Guide (SPRUGQ9). The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three 4 OMAPL138B C6-Integra™ DSP+ARM® Processor Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAPL138B-EP |
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