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OMAP3503DCBCA Datasheet(PDF) 1 Page - Texas Instruments |
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OMAP3503DCBCA Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 264 page  OMAP3515, OMAP3503 www.ti.com SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013 OMAP3515 and OMAP3503 Applications Processors Check for Samples: OMAP3515, OMAP3503 1 OMAP3515 and OMAP3503 Applications Processors 1.1 Features 12 – 256-KB L2 Cache • OMAP3515 and OMAP3503 Devices: • 112KB of ROM – OMAP™ 3 Architecture • 64KB of Shared SRAM – MPU Subsystem • Endianess: • Up to 720-MHz ARM® Cortex™-A8 Core – ARM Instructions – Little Endian • NEON™ SIMD Coprocessor – ARM Data – Configurable – PowerVR® SGX™ Graphics Accelerator (OMAP3515 Device Only) • External Memory Interfaces: • Tile-Based Architecture Delivering up to – SDRAM Controller (SDRC) 10 MPoly/sec • 16- and 32-Bit Memory Controller with • Universal Scalable Shader Engine: Multi- 1GB of Total Address Space threaded Engine Incorporating Pixel and • Interfaces to Low-Power Double Data Vertex Shader Functionality Rate (LPDDR) SDRAM • Industry Standard API Support: • SDRAM Memory Scheduler (SMS) and OpenGLES 1.1 and 2.0, OpenVG1.0 Rotation Engine • Fine-Grained Task Switching, Load – General Purpose Memory Controller (GPMC) Balancing, and Power Management • 16-Bit-Wide Multiplexed Address and • Programmable High-Quality Image Anti- Data Bus Aliasing • Up to 8 Chip-Select Pins with 128-MB – Fully Software-Compatible with ARM9™ Address Space per Chip-Select Pin – Commercial and Extended Temperature • Glueless Interface to NOR Flash, NAND Grades Flash (with ECC Hamming Code • ARM Cortex-A8 Core Calculation), SRAM, and Pseudo-SRAM – ARMv7 Architecture • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, • TrustZone® CPLD, ASICs, and so forth) • Thumb®-2 • Nonmultiplexed Address and Data Mode • MMU Enhancements (Limited 2-KB Address Space) – In-Order, Dual-Issue, Superscalar • System Direct Memory Access (sDMA) Microprocessor Core Controller (32 Logical Channels with – NEON Multimedia Architecture Configurable Priority) – Over 2x Performance of ARMv6 SIMD • Camera Image Signal Processor (ISP) – Supports Both Integer and Floating-Point – CCD and CMOS Imager Interface SIMD – Memory Data Input – Jazelle® RCT Execution Environment – BT.601 (8-Bit) and BT.656 (10-Bit) Digital Architecture YCbCr 4:2:2 Interface – Dynamic Branch Prediction with Branch – Glueless Interface to Common Video Target Address Cache, Global History Decoders Buffer, and 8-Entry Return Stack – Resize Engine – Embedded Trace Macrocell (ETM) Support • Resize Images From 1/4x to 4x for Noninvasive Debug • Separate Horizontal and Vertical Control • ARM Cortex-A8 Memory Architecture: • Display Subsystem – 16-KB Instruction Cache (4-Way Set- Associative) – Parallel Digital Output – 16-KB Data Cache (4-Way Set-Associative) • Up to 24-Bit RGB 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2008–2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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