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OMAP3525-HIREL Datasheet(PDF) 2 Page - Texas Instruments |
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OMAP3525-HIREL Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 262 page  OMAP3525-HiRel, OMAP3530-HiRel SPRS599D – JUNE 2009 – REVISED AUGUST 2010 www.ti.com – Embedded Trace Macrocell (ETM) Support – Parallel Digital Output for Non-Invasive Debug • Up to 24-Bit RGB • ARM Cortex™-A8 Memory Architecture: • HD Maximum Resolution – 16 K-Byte Instruction Cache (4-Way • Supports Up to 2 LCD Panels Set-Associative) • Support for Remote Frame Buffer – 16 K-Byte Data Cache (4-Way Interface (RFBI) LCD Panels Set-Associative) – 2 10-Bit Digital-to-Analog Converters (DACs) – 256 K-Byte L2 Cache Supporting: • 112K-Byte ROM • Composite NTSC/PAL Video • 64K-Byte Shared SRAM • Luma/Chroma Separate Video (S-Video) • Endianess: – Rotation 90-, 180-, and 270-degrees – ARM Instructions - Little Endian – Resize Images From 1/4x to 8x – ARM Data – Configurable – Color Space Converter – DSP Instruction/Data - Little Endian – 8-bit Alpha Blending • External Memory Interfaces: • Serial Communication – SDRAM Controller (SDRC) – 5 Multichannel Buffered Serial Ports • 16, 32-bit Memory Controller With (McBSPs) 1G-Byte Total Address Space • 512 Byte Transmit/Receive Buffer • Interfaces to Low-Power Double Data (McBSP1/3/4/5) Rate (LPDDR) SDRAM • 5K-Byte Transmit/Receive Buffer • SDRAM Memory Scheduler (SMS) and (McBSP2) Rotation Engine • SIDETONE Core Support (McBSP2 and 3 – General Purpose Memory Controller (GPMC) Only) For Filter, Gain, and Mix Operations • 16-bit Wide Multiplexed Address/Data Bus • Direct Interface to I2S and PCM Device and TDM Buses • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin • 128 Channel Transmit/Receive Mode • Glueless Interface to NOR Flash, NAND – Four Master/Slave Multichannel Serial Port Flash (With ECC Hamming Code Interface (McSPI) Ports Calculation), SRAM and Pseudo-SRAM – High-Speed/Full-Speed/Low-Speed USB OTG • Flexible Asynchronous Protocol Control Subsystem (12-/8-Pin ULPI Interface) for Interface to Custom Logic (FPGA, – High-Speed/Full-Speed/Low-Speed Multiport CPLD, ASICs, etc.) USB Host Subsystem • Nonmultiplexed Address/Data Mode • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin (Limited 2K-Byte Address Space) Serial Interface • System Direct Memory Access (sDMA) • Supports Transceiverless Link Logic Controller (32 Logical Channels With (TLL) Configurable Priority) – One HDQ/1-Wire Interface • Camera Image Signal Processing (ISP) – Three UARTs (One with Infrared Data – CCD and CMOS Imager Interface Association [IrDA] and Consumer Infrared – Memory Data Input [CIR] Modes) – RAW Data Interface – Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers – BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface • Removable Media Interfaces: – A-Law Compression and Decompression – Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO) – Preview Engine for Real-Time Image Processing • Comprehensive Power, Reset, and Clock Management – Glueless Interface to Common Video Decoders – SmartReflex™ Technology – Histogram Module/Auto-Exposure, – Dynamic Voltage and Frequency Scaling Auto-White Balance, and Auto-Focus Engine (DVFS) – Resize Engine • Test Interfaces • Resize Images From 1/4x to 4x – IEEE-1149.1 (JTAG) Boundary-Scan Compatible • Separate Horizontal/Vertical Control – Embedded Trace Macro Interface (ETM) • Display Subsystem 2 OMAP3525-HiRel and OMAP3530-HiRel Applications Processor Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): OMAP3525-HiRel OMAP3530-HiRel |
Similar Part No. - OMAP3525-HIREL_16 |
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Similar Description - OMAP3525-HIREL_16 |
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