Charge

Pump

Fastlock

Control

R2_LF

C2_LF

C1_LF

R2pLF

CPout

TRIG2

8

LMX2491

SNAS711 – OCTOBER 2016

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Copyright © 2016, Texas Instruments Incorporated

7.3.5 Fractional Circuitry

The fractional circuitry controls the N divider with delta sigma modulation that supports a programmable first,

second, third, and fourth-order modulator. The fractional denominator is a fully programmable 24-bit denominator

7.3.6 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the R and N dividers and generates a correction voltage

corresponding to the phase error. This voltage is converted to a correction current by the charge pump. The

The charge pump supply voltage on this device, Vcp, can be either run at the Vcc voltage, or up to 5.25 volts to

get higher tuning voltages to present to the VCO.

7.3.7 External Loop Filter

The loop filter is external to the device and is application specific. Texas Instruments website has details on this

at Vcc on www.ti.com.

7.3.8 Fastlock and Cycle Slip Reduction

This PLL has a Fastlock and a cycle slipping reduction feature. The user can enable these two features by

programming FL_TOC to a non-zero value. Every time PLL_N (the feedback divider, register R17 and R16) is

written, the Fastlock feature engages for the prescribed time set in FL_TOC. There are 3 actions that can be

enabled while the counter is running:

1. Change the charge pump current to the desired higher value FL_CPG. Typically this value would be set to

the maximum at 31x. This increases the loop bandwidth and hence reduces lock time.

2. Change the phase detector frequency with FL_CSR to reduce cycle slipping. The phase detector frequency

can be reduced by a factor 2 or 4 to reduce cycle slipping.

3. The loop filter can be configured to have a switchable R2 resistor to increase loop bandwidth and hence

reduce lock time. A resistor R2pLF is added in parallel to R2_LF and connected to the a terminal on the PLL

to use the internal switch. Any of the terminal MUXout, MOD, TRIG1,or TRIG2 can be configured for the

function. The terminal configuration is set as Output TOC Running. Also set the terminal as output inverted

OD (OD for open-drain) so the output will be high impedance in normal operation and act as ground in

Fastlock. The suggested schematic for that feature is shown in Figure 4.

Figure 4. Suggested Schematic to Enable the Variable Loop Bandwidth Filter In Fastlock Mode

Table 2. Fastlock Settings: Charge Pump Gain and Fastlock Pin Status

PARAMETER

NORMAL OPERATION

FASTLOCK OPERATION

Charge Pump Gain

CPG

FL_CPG

Device Pin

(TRIG1, TRIG2, MOD, or MUXout)

High Impedance

Grounded