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LMK04208 Datasheet(PDF) 89 Page - Texas Instruments |
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LMK04208 Datasheet(HTML) 89 Page - Texas Instruments |
89 / 138 page 89 LMK04208 www.ti.com SNAS684 – SEPTEMBER 2016 Product Folder Links: LMK04208 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.6.3.14 Register 27 8.6.3.14.1 PLL1_CP_POL, PLL1 Charge Pump Polarity PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope. A positive slope VCXO increases output frequency with increasing voltage. A negative slope VCXO decreases output frequency with increasing voltage. Table 93. PLL1_CP_POL R27[28] DESCRIPTION 0 Negative Slope VCO/VCXO 1 Positive Slope VCO/VCXO 8.6.3.14.2 PLL1_CP_GAIN, PLL1 Charge Pump Current This bit programs the PLL1 charge pump output current level. Table 94 also illustrates the impact of the PLL1 TRI-STATE bit in conjunction with PLL1_CP_GAIN. Table 94. PLL1_CP_GAIN, 2 Bits R26[27:26] PLL1_CP_TRI R27[5] CHARGE PUMP CURRENT (µA) X 1 Hi-Z 0 (0x00) 0 100 1 (0x01) 0 200 2 (0x02) 0 400 3 (0x03) 0 1600 8.6.3.14.3 CLKinX_PreR_DIV The pre-R dividers before the PLL1 R divider can be programmed such that when the active clock input is switched, the frequency at the input of the PLL1 R divider will be the same. This allows PLL1 to stay in lock without needing to re-program the PLL1 R register when different clock input frequencies are used. This is especially useful in the auto CLKin switching modes. Table 95. CLKinX_PreR_DIV Programming Addresses CLKinX_PreR_DIV PROGRAMMING ADDRESS CLKin1_PreR_DIV R27[23:22] CLKin0_PreR_DIV R27[21:20] Table 96. CLKinX_PreR_DIV, 2 Bits R27[23:22, 21:20] DIVIDE 0 (0x00) 1 1 (0x01) 2 2 (0x02) 4 3 (0x03) 8 |
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