LMK04208 datasheet(82/138 Pages) TI1

Part #	LMK04208

Description	Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

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LMK04208

SNAS684 – SEPTEMBER 2016

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8.6.3.8 Register 15

8.6.3.8.1

MAN_DAC

Sets the DAC value when in manual DAC mode in ~3.2 mV steps.

Table 73. MAN_DAC, 10 Bits

R15[31:22]

DAC VOLTAGE

0 (0x00)

0 × Vcc / 1023

1 (0x01)

1 × Vcc / 1023

2 (0x02)

2 × Vcc / 1023

...

1023 (0x3FF)

1023 × Vcc / 1023

8.6.3.8.2

EN_MAN_DAC

This bit enables the manual DAC mode.

Table 74. EN_MAN_DAC

R15[20]

DAC MODE

0

Automatic

1

Manual

8.6.3.8.3

HOLDOVER_DLD_CNT

Lock must be valid for this many clocks of PLL1 PDF before holdover mode is exited.

Table 75. HOLDOVER_DLD_CNT, 14 Bits

R15[19:6]

EXIT COUNTS

0 (0x00)

Reserved

1 (0x01)

1

2 (0x02)

2

...

16,383 (0x3FFF)

16,383

8.6.3.8.4

FORCE_HOLDOVER

This bit forces the holdover mode.

When holdover is forced, if in fixed CPout1 mode (EN_TRACK = 0 or 1, EN_MAN_DAC = 1) , then the DAC will

set the programmed MAN_DAC value. If in tracked CPout1 mode (EN_TRACK = 1, EN_MAN_DAC = 0,

EN_VTUNE_RAIL_DET = 0), then the DAC will set the current tracked DAC value.

Setting FORCE_HOLDOVER does not constitute a clock input switch event unless DISABLE_DLD1_DET = 0,

since when in holdover mode, PLL1_DLD = 0 will trigger the clock input switch event.

Table 76. FORCE_HOLDOVER

R15[5]

HOLDOVER

0

Disabled

1

Enabled

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