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DSC400-2302Q0001KI1T Datasheet(PDF) 6 Page - Microchip Technology |
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DSC400-2302Q0001KI1T Datasheet(HTML) 6 Page - Microchip Technology |
6 / 20 page DSC400 DS20005612A-page 6 2016 Microchip Technology Inc. 4.0 TERMINATION SCHEMES 4.1 LVPECL FIGURE 4-1: Typical LVPECL Termination Scheme. Note 1: LVPECL applicable to extended commercial temperature only. 2: See the Output Waveform section for more information. 3: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 4: Period jitter includes crosstalk from adjacent output. VDD 100 Ω 130 Ω 82 Ω 130 Ω 82 Ω TABLE 4-1: LVPECL OUTPUTS (Note 1) Parameter Symbol Min. Typ. Max. Units Condition Output Logic Levels VOH VDD – 1.08 — — V Output Logic High, RL = 50Ω to VDD–2V VOL —— VDD – 1.55 Output Logic Low, RL = 50Ω to VDD–2V Peak-to-Peak Output Swing — — 800 — mV Single-Ended Output Transition Time (Note 2) tR — 250 — ps Rise Time. 20% to 80%; RL = 50Ω to VDD–2V tF — 250 — Fall Time. 20% to 80%; RL = 50Ω to VDD–2V Frequency f0 2.3 — 460 MHz Single Frequency Output Duty Cycle SYM 48 — 52 % Differential IO Supply Current (Note 3) IDDIO — 35 38 mA Per Output at 125 MHz Period Jitter (Note 4) JPER —2.5 — psRMS CLK(0:3) = 156.25 MHz Integrated Phase Noise JPH —0.25— psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.38 — 100 kHz to 20 MHz @ 156.25 MHz — 1.7 2 12 kHz to 20 MHz @ 156.25 MHz |
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