128M GDDR SDRAM

K4D261638F

- 9 -

Rev. 1.2 (Jan. 2004)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

DLL Enable

0

Enable

1

Disable

0MRS

1EMRS

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

Output Driver Impedence Control

01

Weak

11

Matched

RFU

1

RFU

D.I.C

RFU

D.I.C

DLL

Mode Register