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ISD5116S Datasheet(PDF) 28 Page - Winbond

Part No. ISD5116S
Description  Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
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Maker  WINBOND [Winbond]
Homepage  http://www.winbond.com

ISD5116S Datasheet(HTML) 28 Page - Winbond

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Page 27
The Digital Write function allows the user to select a portion of the array to be used as digital
memory. The partition between analog and digital memory is left up to the user. A page can
only be either Digital or Analog, not both. The minimum addressable block of memory in the
digital mode is one block or 64 bits, when reading or writing. The address sent to the device
is the 11-bit row (or page) address with the 5-bit scan (or block) address. However, one must
send a Digital Erase before attempting to change digital data on a page. This means that
even when changing only one of the 32 blocks, all 32 will need to be rewritten to the page.
After the address is entered, the data is sent in one-byte packets followed by an I
acknowledge generated by the chip. Data for each block is sent MSB first. The data transfer
is ended when the master generates an I
2C STOP condition. If only a partial block of data is
sent before the STOP condition, zero is “written” in the remaining bytes; that is, they are left at
the erase level. An erased page (row) will be read as all zeros. The device can buffer up to
two blocks of data. If the device is unable to accept more data due to the internal write
process, the SCL line will be held LOW indicating to the master to halt data transfer. If the
device encounters an overflow condition, it will respond by generating an interrupt condition
and an I
2C Not Acknowledge signal after the last valid byte of data. Once data transfer is
terminated, the device needs up to two cycles (64 us) to complete its internal write cycle
before another command is sent. If an active command is sent before the internal cycle is
finished, the part will hold SCL LOW until the current command is finished.
The Digital Read command utilizes the combined I
2C command format. That is, a command is
sent to the chip using the write data direction. Then the data direction is reversed by sending
a repeated start condition, and the slave address with R/W set to 1. After this, the slave
device (ISD5116) begins to send data to the master until the master generates a Not
Acknowledge. If the part encounters an overflow condition, the INT pin is pulled LOW. No
other communication with the master is possible due to the master generating ACK signals.
As with Digital Write, Digital Read can be done a “block” at a time. Thus, only 64 bits need be
read in each Digital Read command sequence.
The Digital Erase command can only erase an entire page at a time. This means that only the
D1 command needs to include the 11-bit page address; the 5-bit for block address are left at
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if
a block has been previously written then the entire page of 2048 bits must be erased in order
to re-write (or change) a block.
A sequence might be look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page

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