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ISD5116EI Datasheet(PDF) 45 Page - Winbond |
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ISD5116EI Datasheet(HTML) 45 Page - Winbond |
45 / 57 page October 2000 Page 44 I 2C Interface Timing STANDARD-MODE FAST-MODE PARAMETER SYMBOL MIN. MAX. MIN. MAX. UNIT SCL clock frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD; STA 4.0 - 0.6 - µs LOW period of the SCL clock tLOW 4.7 - 1.3 - µs HIGH period of the SCL clock tHIGH 4.0 - 0.6 - µs Set-up time for a repeated START condition tSU; STA 4.7 - 0.6 - µs Data set-up time tSU; DAT 250 - 100 (1) -ns Rise time of both SDA and SCL signals tr - 1000 20 + 0.1Cb (2) 300 ns Fall time of both SDA and SCL signals tf - 300 20 + 0.1Cb (2) 300 ns Set-up time for STOP condition tSU; STO 4.0 - 0.6 - µs Bus-free time between a STOP and START condition tBUF 4.7 - 1.3 - µs Capacitive load for each bus line Cb - 400 - 400 pF Noise margin at the LOW level for each connected device (including hysteresis) VnL 0.1 VDD - 0.1 VDD -V Noise margin at the HIGH level for each connected device (including hysteresis) VnH 0.2 VDD - 0.2 VDD -V 1. A Fast-mode I 2C-interface device can be used in a Standard-mode I2C-interface system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I 2C -interface specification) before the SCL line is released. 2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed. |
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