Electronic Components Datasheet Search |
|
DSC2031FI5 Datasheet(PDF) 4 Page - Micrel Semiconductor |
|
DSC2031FI5 Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 6 page ______________________________________________________________________________________________________________________________________________ DSC2031 Page 4 MK-Q-B-P-D-12042607-2 DSC2031 Low-Jitter Configurable Dual LVDS-CMOS Oscillator Specifications (Unless specified otherwise: T=25° C, max CMOS drive strength) Notes: 1. Pin 4 VDD should be filtered with 0.01uf capacitor. 2. Output is enabled if Enable pad is floated or not connected. 3. tsu is time to stable output frequency after VDD is applied and outputs are enabled. 4. Output Waveform and Test Circuit figures below define the parameters. 5. Period Jitter includes crosstalk from adjacent output. Parameter Condition Min. Typ. Max. Unit Supply Voltage1 VDD 2.25 3.6 V Supply Current IDD EN pin low – outputs are disabled 21 23 mA Supply Current2 IDD EN pin high – outputs are enabled LVDS: RL=100Ω, FO1=125 MHz CMOS: CL=15pF, FO2=75 MHz 49 mA Frequency Stability Δf Includes frequency variations due to initial tolerance, temp. and power supply voltage ±10 ±25 ±50 ppm Aging Δf 1 year @25°C ±5 ppm Startup Time3 tSU T=25°C 5 ms Input Logic Levels Input logic high Input logic low VIH VIL 0.75xVDD - - 0.25xVDD V Output Disable Time4 tDA 5 ns Output Enable Time tEN 20 ns Pull-Up Resistor2 Pull-up exists on all digital IO 40 kΩ LVDS Output Output Offset Voltage R=100Ω Differential 1.125 1.4 V Delta Offset Voltage 50 mV Pk to Pk Output Swing Single-Ended 350 mV Output Transition time4 Rise Time Fall Time tR tF 20% to 80% RL=100Ω, CL= 2pF (to GND) 200 350 ps Frequency f0 Single Frequency 2.3 460 MHz Output Duty Cycle SYM Differential 48 52 % Period Jitter5 JPER FO1=125 MHz 2.5 psRMS Integrated Phase Noise JCC 200kHz to 20MHz @156.25MHz 100kHz to 20MHz @156.25MHz 12kHz to 20MHz @156.25MHz 0.28 0.4 1.7 2 psRMS CMOS Output Output Logic Levels Output logic high Output logic low VOH VOL I=±6mA 0.9xVDD - - 0.1xVDD V Output Transition time4 Rise Time Fall Time tR tF 20% to 80% CL=15pf 1.1 1.3 2 2 ns Frequency f0 Commercial/Industrial temp range 2.3 170 MHz Output Duty Cycle SYM 45 55 % Period Jitter5 JPER FO2=125 MHz 3 psRMS Integrated Phase Noise JCC 200kHz to 20MHz @ 125MHz 100kHz to 20MHz @ 125MHz 12kHz to 20MHz @ 125MHz 0.3 0.38 1.7 2 psRMS |
Similar Part No. - DSC2031FI5 |
|
Similar Description - DSC2031FI5 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |