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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT5V9910A

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

SEPTEMBER 2001

2001

Integrated Device Technology, Inc.

DSC 5847/1

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Eight zero delay outputs

• <250ps of output to output skew

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 15MHz to 85MHz

• 3 skew grades:

• 3-level inputs for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps peak-to-peak

• Available in SOIC package

FUNCTIONAL BLOCK DIAGRAM

G ND/sO E

REF

FS

PLL

FB

IDT5V9910A

3.3V LOW SKEW

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

DESCRIPTION:

The IDT5V9910A is a high fanout phase locked-loop clock driver

intended for high performance computing and data-communications appli-

cations. It has eight zero delay LVTTL outputs.

When the GND/

sOE pin is held low, all the outputs are synchronously

enabled. However, if GND/

PE is held low, all the outputs are synchronized with the negative edge of

REF.

The FB signal is compared with the input REF signal at the phase detector

in order to drive the VCO. Phase differences cause the VCO of the PLL to

adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the phase

detector. The loop filter transfer function has been chosen to provide minimal

jitter (or frequency variation) while still providing accurate responses to input

frequency changes.