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MC100EL32DR2G Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100EL32DR2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC10EL32, MC100EL32 www.onsemi.com 2 4 3 Figure 1. Logic Diagram and Pinout Assignment 1 2 5 6 7 8 Q VEE VCC Q CLK VBB R ÷2 Reset CLK Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Clock Inputs* Reset ECL Asynch Reset* Q, Q ECL Data Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply *Pins will default low when left open. Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI ≤ VCC VI ≥ VEE 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W Tsol Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) |
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