MC10EL15, MC100EL15

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2

Figure 1. Logic Diagram and Pinout Assignment

Q0

Q1

Q2

Q3

15

16

14

13

12

11

10

2

1

34567

9

8

Q3

Q2

Q1

Q0

EN

SCLK

CLK

CLK

SEL

D

Q

1

PIN

FUNCTION

CLK, CLK

ECL Diff Clock Inputs

SCLK

ECL Scan Clock Input

EN

ECL Sync Enable

SEL

ECL Clock Select Input

ECL Diff Clock Outputs

Reference Voltage Output

Positive Supply

Negative Supply

Table 1. PIN DESCRIPTION

CLK*

L

H

X

X

X

SCLK*

X

X

L

H

X

SEL*

L

L

H

H

X

EN*

L

L

L

L

H

Q

L

H

L

H

L(1)

Table 2. FUNCTION TABLE

*Pins will default low when left open.

1. On next negative transition of CLK or SCLK

0

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 KW

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1 kV

> 100 V

2kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

103

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.