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DG189 Datasheet(PDF) 1 Page - Vishay Siliconix

Part No. DG189
Description  High-Speed Drivers with Dual SPDT JFET Switches
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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DG189 Datasheet(HTML) 1 Page - Vishay Siliconix

   
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*Common to Substrate and Case
Flat Package
S4
S3
D4
D3
D2
D1
S2
S1
IN2
IN1
V+
V−*
VL
VR
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Top View
D1
S1
NC
Dual-In-Line
IN1
D3
V−
S3
VR
S4
VL
D4
V+
NC
IN2
D2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
Refer to JAN38510 Information, Military Section
DG189/190/191
Vishay Siliconix
Document Number: 70034
S-51140—Rev. D, 20-Jun-05
www.vishay.com
1
High-Speed Drivers with Dual SPDT JFET Switches
FEATURES
BENEFITS
APPLICATIONS
D Constant On-Resistance Over
Entire Analog Range
D Low Leakage
D Low Crosstalk
D Rad Hardness
D Low Distortion
D Eliminates Large Signal Errors
D High Precision
D High Bandwidth Capability
D Fault Protection
D Audio Switching
D Video Switching
D Sample/Hold
D Guidance and Control Systems
D Aerospace
DESCRIPTION
The DG189/190/191 are precision dual single-pole,
double-throw (SPDT) analog switches designed to provide
accurate switching of video and audio signals. This series is
ideally suited for applications requiring a constant
on-resistance over the entire analog range.
The major difference in the devices is the on-resistance
(DG189—10 W, DG190—30 W, DG191—75 W). Reduced
errors are achieved through low leakage current (ID(on)
< 2 nA). Applications which benefit from the flat JFET
on-resistance include audio switching, video switching, and
data acquisition.
To achieve fast and accurate switch performance, each device
comprises four n-channel JFET transistors and a TTL
compatible bipolar driver. The driver is designed to achieve
break-before-make
switching
action,
eliminating
the
inadvertent shorting between channels and the crosstalk
which would result. In the on state, each switch conducts
current equally well in either direction. In the off condition, the
switches will block up to 20 V peak-to-peak, with feedthrough
of less than −60 dB at 10 MHz.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
TRUTH TABLE
Logic
SW1, SW2
SW3, SW4
0
OFF
ON
1
ON
OFF
Logic “0” v 08 V
Logic “0” v 0.8 V
Logic “1” w 24 V
g
Logic “1” w 2.4 V


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