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CS9211 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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CS9211 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 62 page  Revision 2.1 9 www.national.com 2.2 SIGNAL DESCRIPTIONS 2.2.1 Pixel Port Interface Signals Signal Name Pin No. Type (Drive) Description RED[5:0] 96, 86, 85, 78, 79, 76 I Red Pixel Channel These six pins are the red component of the pixel port input. The six most significant bits of the pixel port (FP_DATA[17:12] on an 18-bit pixel port) from the CS5530A are connected to these pins. RED5 is the MSB (most signifi- cant bit) and RED0 is the LSB (least significant bit). GREEN[5:0] 100, 98, 94, 87, 92, 93 I Green Pixel Channel These six pins are the green component of the pixel port input. The six mid- dle bits of the pixel port (FP_DATA[11:6] on an 18-bit pixel port) from the CS5530A are connected to these pins. GREEN5 is the MSB and GREEN0 is the LSB. BLUE[5:0] 88, 84, 81, 83, 82, 80 I Blue Pixel Channel These six pins are the blue component of the pixel port input. The six least significant bits of the pixel port (FP_DATA[5:0] on an 18-bit pixel port) from the CS5530A are connected to these pins. BLUE5 is the MSB and BLUE0 is the LSB. ENA_DISP 95 I Active Display Enable This input is asserted when the pixel data stream is presenting valid display data to the pixel port. ENA_VDDIN 77 I Input VDD Enable When this input is asserted high, it indicates that the CS9211 should apply voltage to the LCD panel. FP_VDDEN (pin 34) follows this assertion if exter- nal power sequencing is selected; it is ignored if internal power sequencing is selected. ENA_LCDIN 101 I Input LCD Enable When this input is asserted high, it indicates that the CS9211 should drive the contrast voltage to the LCD panel. FP_VCONEN (pin 35) follows this assertion if external power sequencing is selected; it is ignored if internal power sequencing is selected. DOTCLK 75 I DOT Clock This signal is the pixel clock from the video controller within the CS550A. It clocks data in from the pixel port on the rising edge. Additionally, this signal is used as the input clock for the entire CS9211 device. This clock must be running at all times after reset for the CS9211 to function correctly. FP_HSYNC 97 I Flat Panel Horizontal Sync Input When the input data stream is in a horizontal blanking period, this input is asserted. It is a pulse used to synchronize display lines and to indicate when the pixel data stream is not valid due to blanking. FP_VSYNC 99 I Flat Panel Vertical Sync Input When the input data stream is in a vertical blanking period, this input is asserted. It is a pulse used to synchronize display frames and to indicate when the pixel data stream is not valid due to blanking. |
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