Micrel, Inc.

DSC2111FL2-E0018

4

4

5

Parameter

Symbol

Condition

Min.

Typ.

Max.

Units

Supply Voltage¹

VDD

2.25

3.6

V

Supply Voltage (CLK2)¹

VDD2

1.65

3.6

V

Supply Current

IDD

OE pin low - outputs are disabled

21

23

mA

Supply Current²

IDD

OE pin high - outputs are enabled

CL = 15pF, F01 = F02 = 125MHz

32

mA

Frequency Stability

F

Includes frequency variation due to initial

tolerance, temp. and power supply voltage

±25

ppm

Aging

F

First year (@ 25°C)

±5

ppm

Startup Time³

tSU

T = 25°C

5

ms

Input Logic Levels

Input Logic High

Input Logic Low

VIH

VIL

0.75 x VDD

-

-

0.25 x VDD

V

Output Disable Time

tDA

5

ns

Output Enable Time

tEN

20

ns

Pull-Up Resistor²

Pull-up exists on all digital IO

40

kOhms

LVCMOS Outputs

Output Logic Levels

Output Logic High

Output Logic Low

VOH

VOL

I = ±6mA

0.9 x VDD

-

-

0.1 x VDD

V

Output Transition Time

Rise Time

Fall Time

tR

tF

20% to 80%

CL = 15pF

1.1

1.4

2

2

ns

Frequency

CLK1

CLK2

[FS] = [1]

25

125

MHz

Output Duty Cycle

SYM

45

55

%

Period Jitter

JPER

F01 = F02 = 125MHz

3

psRMS

Integrated Phase Noise

JPH

200kHz to 20MHz @ 125MHz

100kHz to 20MHz @ 125MHz

12kHz to 20MHz @ 125MHz

0.3

0.38

1.7

2

psRMS

Notes:

1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.

2. Output is enabled if OE pin is floated or not connected.

3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.

4. Output Waveform and Test Circuit figures below define the parameters.

5. Period Jitter includes crosstalk from adjacent output.

May 11, 2015

4

Revision 1.0

tcghelp@micrel.com or (408) 955-1690

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