Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

AS7C1025 Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation

Part No. AS7C1025
Description  5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout)
Download  9 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
Logo 

AS7C1025 Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation

   
Zoom Inzoom in Zoom Outzoom out
 6 / 9 page
background image
®
AS7C1025
AS7C31025
3/23/01; v.1.0
Alliance Semiconductor
P. 6 of 9
Data retention characteristics (over the operating range)13
Data retention waveform
AC test conditions
Notes
1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2
This parameter is sampled, but not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A, B, and C.
4tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
5
This parameter is guaranteed, but not 100% tested.
6WE is High for read cycle.
7CE and OE are Low for read cycle.
8
Address valid prior to or coincident with CE transition Low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, where C=5pF.
Parameter
Symbol
Test conditions
Min
Max
Unit
VCC for data retention
VDR
VCC = 2.0V
CE
≥ V
CC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
2.0
V
Data retention current
ICCDR
–500
µA
Chip enable to data retention time
tCDR
0–
ns
Operation recovery time
tR
tRC
–ns
Input leakage current
| I
LI |
–1
µA
VCC
CE
tR
tCDR
Data retention mode
VCC
VCC
VDR ≥ 2.0V
VIH
VIH
VDR
255W
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C(14)
320W
DOUT
GND
+3.3V
168W
Thevenin equivalent:
DOUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W
C(14)
480W
DOUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns


Html Pages

1  2  3  4  5  6  7  8  9 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn