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ADS5204 Datasheet(PDF) 6 Page - Texas Instruments

Part No. ADS5204
Description  DUAL 10 BIT 40MSPS LOW POWER ANALOG TO DIGITAL CONVERTER WITH PGA
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5204 Datasheet(HTML) 6 Page - Texas Instruments

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ADS5204
SBAS268A – JUNE 2002 – REVISED JULY 2002
www.ti.com
6
TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Clock Rate
fCLK
1
80
MHz
Conversion Rate
1
40
MSPS
Clock Duty Cycle (40MHz)
45
50
55
%
Clock Duty Cycle (80MHz)
42
50
58
%
Output Delay Time
td(o)
CL = 10pF
9
14
ns
Mux Setup Time
ts(m)
9
10.4
ns
Mux Hold Time
th(m)
CL = 10pF
1.7
2.1
ns
Output Setup Time
ts(o)
CL = 10pF
9
10.4
ns
Pipeline Delay (latency, channels A and B)
td(pipe)
MODE = 0, SELB = 0
8
CLK Cycles
Pipeline Delay (latency, channels A and B)
td(pipe)
MODE = 1, SELB = 0
4
CLK Cycles
Pipeline Delay (latency, channel A)
td(pipe)
MODE = 0, SELB = 1
8
CLK Cycles
Pipeline Delay (latency, channel B)
td(pipe)
MODE = 0, SELB = 1
9
CLK Cycles
Pipeline Delay (latency, channel A)
td(pipe)
MODE = 1, SELB = 1
8
CLK Cycles
Pipeline Delay (latency, channel B)
td(pipe)
MODE = 1, SELB = 1
9
CLK Cycles
Output Hold Time
th(o)
CL = 10pF
1.5
2.2
ns
Aperture Delay Time
td(a)
3
ns
Aperture Jitter
tJ(a)
1.5
ps, rms
Disable Time, OE Rising to Hi–Ztdis
5
8
ns
Enable Time, OE Falling to Valid Data
ten
5
8
ns
(1) All internal operations are performed at a 40MHz clock rate.
SERIAL INTERFACE TIMING
PARAMETER
MIN
TYP
MAX
UNIT
Maximum Clock Rate
fSCLK
20
MHz
SCLK Pulse Width HIGH
tWH
25
ns
SCLK Pulse Width LOW
tWH
25
ns
Setup Time, CS LOW Before First Negative SCLK Edge
tSU(CS_CK)
5
ns
CS HIGH Width
tWH(CS)
10
ns
Setup Time, 16th Negative SCLK Edge before CS Rising Edge
tSU(C16_CK)
5
ns
Setup Time, Data Ready Before SCLK Falling Edge
tSU(D)
5
ns
Hold Time, Data Held Valid After SCLK Falling Edge
tSU(H)
5
ns
TIMING OPTIONS
OPERATING MODE
MODE
SELB
TIMING DIAGRAM FIGURE
80MHz Input Clock, Dual-Bus Output, COUT = 40MHz
0
0
1
40MHz Input Clock, Dual-Bus Output, COUT = 40MHz
1
0
2
80MHz Input Clock, Single-Bus Output, COUT = 40MHz
0
1
3
80MHz Input Clock, Single-Bus Output, COUT = 80MHz
1
1
4


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