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ADP3204 Datasheet(PDF) 4 Page - Analog Devices

Part No. ADP3204
Description  3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP3204 Datasheet(HTML) 4 Page - Analog Devices

 
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REV. 0
–4–
ADP3204
NOTES
1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2 Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V
COREFB, BAD = 1.0 V at VVID = 1.25 V setting) to the
COREFB pin right after the moment that
BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (V
COREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good-window (V COREFB, GOOD = 1.25 V) right after the moment
that
BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.
3 Guaranteed by design
4 Measured from 50% of VID code transition amplitude to the point where V
DACOUT settles within
±1% of its steady state value.
5 Measured between DACRAMP and DACOUT pins.
6 40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
7 Measured between the 30% and 70% points of the output voltage swing.
8 DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
9 COREFB pin has a resistor divider to GND whose resistance is 41.3 k
(typ), guaranteed by design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SHIFT SETTING
Battery-Shift Current
IRAMPB, ICS+B
VVID = 1.25 V
–92.5
–100
–107.5
mA
IBSHIFT = –100
µA, BOM = L
DPSLP = H
Battery-Shift Reference Voltage
VBSHIFT
VDAC
V
Deep Sleep-Shift Current
IRAMPD, ICS+D
VVID = 1.25 V
–92.5
–100
–107.5
mA
IDSHIFT = –100
µA, BOM = H
DPSLP = L
Deep Sleep-Shift Reference
VDSHIFT
VDAC
V
Voltage
Deeper Sleep-Shift Current
IREGDPR
IDPRSHIFT = –100
µA, DPRSLP = H –90
–100
–110
µA
ICOREFBDPR
8
VVID = 1.25 V,
110
130
150
µA
IDPRSHIFT = –100
µA,
DPRSLP = H
Deeper Sleep-Shift Reference
VDPRSHIFT
VDAC
V
Voltage
SHIFT CONTROL INPUTS
BOM Threshold
VBOM
VCC/2
V
(CMOS Input)
DPSLP Threshold
VDSLP
VCC/2
V
(CMOS Input)
DPRSLP Mode Threshold
8
VDPRSLP
VCC/2
V
(CMOS Input)
LOW SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
VDRVLSD
DPRSLP = H
0
0.4
V
DPRSLP = L
0.7 VCC
VCC
V
Output Current
IDRVLSD
DPRSLP = H, VDRVLSD = 1.5 V
+0.4
mA
DPRSLP = L, VDRVLSD = 1.5 V
–0.4
mA
OVER/REVERSE VOLTAGE
PROTECTION CORE FEEDBACK
Overvoltage Threshold
VCOREFB, OVP
9
VCOREFB
2.0
V
Reverse-Voltage Threshold
VCOREFB, RVP
9
VCOREFB
–0.3
V
Output Current
ICLAMP
VCOREFB = 2.2 V, VCLAMP = 1.5 V
10
µA
(Open-Drain Output)
VCOREFB = VDAC, VCLAMP = 1.5 V
2
6
mA


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