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TAS5036 Datasheet(PDF) 15 Page - Texas Instruments |
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TAS5036 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 49 page  Architecture Overview 10 SLES044B—November 2002 TAS5036 2.1.5 PLL Filter A low jitter PLL produces the internal timing of the TAS5036 (when in master mode), the master clock, SCLK, and LRCLK. Connections for the PLL external loop filter are provided through PLL_FLT_OUT and PLL_FLT_RET as shown in Figure 2–2. PLL_FLT_OUT TAS5036 PLL_FLT_RET 220 Ω 47 nF 4.7 nF Figure 2–2. External PLL Loop Filter 2.1.6 DCLK DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5036A uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I2C addressable registers, DCLK clock cycles are used to specify Interchannel delay and to detect when the MCLK is frequency is drifting. Table 2–4 DCLK shows the relationship between Sample Rate, MCLK and DCLK. Table 2–4. DCLK FS (kHz) MCLK (MHz) DCLK (MHz) DCK Period (ns) 32 8.1920 65.5360 15.3 44.1 11.2896 90.3168 11.1 48 12.2880 98.3040 10.2 88 22.5280 90.1120 11.1 96 24.5760 98.3040 10.2 192 49.1520 98.3040 10.2 2.1.7 Serial Data Interface The TAS5036 operates as a slave only/receive only serial data interface in all modes. The TAS5036 has three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The serial audio data is in MSB first; 2s complement format. The serial data interfaces of the TAS5036 can be configured in right justified, I2S, left-justified, or DSP modes. This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample rates. The serial data interface format is specified using the data interface control register. The supported word lengths are shown in Table 2–5. During normal operating conditions if the serial data interface settings change state, an error recovery sequence is initiated. |
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