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LTC4355 Datasheet(PDF) 11 Page - Linear Integrated Systems |
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LTC4355 Datasheet(HTML) 11 Page - Linear Integrated Systems |
11 / 20 page LTC4419 11 4419f For more information www.linear.com/LTC4419 applicaTions inForMaTion The first step to avoid these issues is to minimize parasitic inductance and resistance in the power path. Guidelines are given in the layout section for minimizing parasitic inductance on the printed circuit board (PCB). External to the PCB, twist the power and ground wires together to minimize inductance. Second, use a bypass capacitor at the input to limit input voltage overshoot during LTC4419 power path turn off. A few micro farads is sufficient for most applications. When hot plugging supplies with large parasitic inductances, it is possible for the R-L-C tank to ring to more than twice the nominal supply voltage. Wall adapters and batteries typicallyhaveenoughloss(i.e.seriesresistance)toprevent ringing of this magnitude. However, if this is a problem, snub input capacitor CSN1 with resistor RSN1, typically 0.5Ω. Place this network close to the supply pin. Third, if an input capacitor is not permissible, use a TVS (such as SMAJ16CA) in applications when supply pin transients can exceed 24V. Use a bidirectional TVS in applications requiring reverse input protection. Note that a TVS does not address droop and motorboating, which are solved only by input bypassing. During normal operation, the LTC4419 limits power path current to < 1.6A and internal circuitry prevents OUT from ringing below ground during power path turn off. This is also true for output shorts when the short is close to the LTC4419’s OUT pin. However, if the output is shorted through a long wire, current in the wire inductance (LPAR2 in Figure 3) builds up due to the discharge of COUT1 and can be much higher than 1.6A. This current causes the OUT pin to ring below its −0.3V absolute maximum rating once COUT1 has been fully discharged. For this special case, split the output capacitor between COUT1 and COUT2 and make COUT1 small. Snub COUT1 with resistor RSN2 to damp R-L-C ringing if required. Size COUT2 to obtain the requiredtotaloutputcapacitance.Alsoaddadiodebetween OUT and ground close to the LTC4419 to clamp negative ringing if the OUT pin rings below –0.3V. Increasing CMP1 and CMP2 Hysteresis Insomeapplications,built-inCMP1hysteresismaybeinsuf- ficient. In such cases, CMP1 hysteresis can be increased as shown in Figure 4. Hysteresis at the monitored input VMON with R8 present and assuming R9 << R8 is given by: VHYST = VHYSTC • R3 R1||R3||R8 + VPU • R3 R8 (10) whereVHYSTCandVTHCarefoundintheElectricalCharacter- isticstableandaretypically10mVand0.387Vrespectively. Account for supply VPU and resistor R8 when calculating rising and falling thresholds of monitored input VMON. Supply Impedance and ADJ Comparator Hysteresis In some applications, V1 could be supplied by a battery packwithhighESRorthroughalongcablewithappreciable series resistance. Load current, IOUT, flowing through this resistance reduces the monitored V1 voltage by: ∆V1 = IOUT • RESR (11) V1 OUT 4419 F03 COUT1 1µF D1 1N5818 CSN1 5µF RSN1 0.5 LPAR1 OPTIONAL LPAR2 OUT V1 LTC4419 RSN2 1 OPTIONAL COUT2 10µF Figure 3. Recommended Inductive Transient Suppression Circuitry CMP1 VMON VPU LTC4419 R8 R3 R1 R9 CMPOUT1 4419 F04 Figure 4. Increasing CMP1 Hysteresis |
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