IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC

IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC

Integrated Silicon Solution, Inc.- www.issi.com

Rev. C1

09/30/2015

1

128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH

SRAM

OCTOBER 2015

FEATURES



Internal self-timed write cycle



Individual Byte Write Control and Global Write



Clock controlled, registered address, data and

control



Burst sequence control using MODE input



Three chip enable option for simple depth

expansion and address pipelining



Common data inputs and data outputs



Auto Power-down during deselect



Single cycle deselect



Snooze MODE for reduced-power standby



JEDEC 100-pin QFP, 165-ball BGA and 119-ball

BGA packages



Power supply:







JTAG Boundary Scan for BGA packages



Industrial and Automotive temperature support



Lead-free available



Error Detection and Error Correction

DESCRIPTION

The 4Mb product family features high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and

networking applications. The

IS61(64)LF/VF12836EC are

organized as

131,072 words by 36bits. The

IS61(64)LF/VF12832EC are organized as 131,072 words by

32bits. The

IS61(64)LF/VF25618EC are organized as 262,144

words by 18 bits. Fabricated with ISSI's advanced CMOS

technology, the device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (/BWE) input combined with one or more

individual byte write signals (/BWx). In addition, Global

Write (/GW) is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either /ADSP (Address Status

Processor) or /ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the /ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order.

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

-6.5

-7.5

Units

tKQ

Clock Access Time

6.5

7.5

ns

tKC

Cycle time

7.5

8.5

ns

Frequency

133

117

MHz

Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances