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SN75LVPE801

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SLLSEW8 – SEPTEMBER 2016

Product Folder Links: SN75LVPE801

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Copyright © 2016, Texas Instruments Incorporated

(1)

G = Ground, I = Input, O = Output, P = Power

5 Description (continued)

Two de-emphasis levels can be selected on the transmit side to provide 0 dB or 1.2 dB of additional high-

frequency loss compensation at the output.

and removal, unpowered plug and removal, powered plug and removal, or surprise plug and removal.

(1) Requires use of AC coupling capacitors at differential inputs and outputs.

6 Pin Configuration and Functions

DRF Package

8-Pin WSON

Top View

Pin Functions

PIN

DESCRIPTION

NAME

NO.

HIGH SPEED DIFFERENTIAL I/O

RX+

2

I

Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual

termination resistor circuit.

RX–

3

I

TX+

7

O

Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by

dual termination resistor circuit.

TX–

6

O

CONTROL PINS

EQ

4

I

Selects equalization settings per Table 1. Internally tied to GND.

DE

8

I

Selects de-emphasis settings per Table 1. Internally tied to GND.

POWER

1

P

Positive supply must be 3.3 V ±10%

GND

5

G

Supply ground