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IS66WVE1M16EALL-70BLI Datasheet(PDF) 21 Page - Integrated Silicon Solution, Inc |
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IS66WVE1M16EALL-70BLI Datasheet(HTML) 21 Page - Integrated Silicon Solution, Inc |
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21 IS66/67WVE1M16EALL/EBLL/ECLL IS66/67WVE1M16TALL/TBLL/TCLL Rev. C | Oct. 2015 www.issi.com - SRAM@issi.com Description Conditions Symbol TYP MAX Unit Deep Power-Down (ALL/CLL) VIN=VDDQ or 0V; +25°C ZZ# = 0V, CR[4] = 0 Izz 3 10 uA Deep Power-Down (BLL) VIN=VDDQ or 0V; +25°C ZZ# = 0V, CR[4] = 0 Izz 10 20 uA Table 10. Deep Power-Down Specifications Description Conditions Symbol MIN MAX Unit Note Input Capacitance TC=+25°C; f=1Mhz; VIN=0V CIN 2.0 6.5 pF 1 Input/Output Capacitance (DQ) CIO 3.5 6.5 pF 1 Table 11. Capacitance Notes: 1. These parameters are verified in device characterization and are not 100% tested. VDDQ/23 Output Figure 8. AC Input/Output Reference Waveform Test Points ∫∫ ∫∫ VDDQ/22 Input1 VDDQ VSS Notes: 1. AC test inputs are driven at VDDQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VDDQ/2. 3. Output timing ends at VDDQ/2. DUT 30pF 50Ω VDDQ/2 Test Point Figure 9. Output Load Circuit |
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