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IS66WVE1M16EALL-70BLI Datasheet(PDF) 14 Page - Integrated Silicon Solution, Inc

Part No. IS66WVE1M16EALL-70BLI
Description  16Mb Async/Page PSRAM
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS66WVE1M16EALL-70BLI Datasheet(HTML) 14 Page - Integrated Silicon Solution, Inc

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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Rev. C | Oct. 2015
www.issi.com - SRAM@issi.com
Software Access Sequence
The contents of the CR can be read or modified using a software access sequence. The
nature of this access mechanism can potentially eliminate the need for the ZZ# ball.
If the software-access mechanism is used, ZZ# can simply be tied to VDDQ; the port line
typically used for ZZ# control purposes will no longer be required. However, ZZ# should
not be tied to VDDQ if the system will use DPD; DPD cannot be enabled or disabled using
the software-access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed
by two WRITE operations (see Figure 6). The READ sequence is virtually identical
except that an asynchronous READ is performed during the fourth operation (see
Figure 7).
The address used during all READ and WRITE operations is the highest address of the
PSRAM device being accessed (FFFFFh); the content of this address is not changed by
using the software-access sequence. The data bus is used to transfer data into or out of
bit[15:0] of the CR.
Writing to the CR using the software-access sequence modifies the function of the ZZ#
ball. After the software sequence loads the CR, the level of the ZZ# ball no longer enables
PAR operation. PAR operation is updated whenever the software-access sequence loads
a new value into the CR. This ZZ# functionality will remain active until the next time the
device is powered up. The operation of the ZZ# ball is not affected if the software-access
sequence is only used to read the contents of the CR. Use of the software-access sequence
does not affect the performance of standard (ZZ#-controlled) CR loading.
Figure 6 : Configuration Register Write
Notes :
1. CR : 0000h
MAX
ADDRESS
OUTPUT
DATA
MAX
ADDRESS
OUTPUT
DATA
MAX
ADDRESS
MAX
ADDRESS
CR
VALUE IN
*Note1
OE#
Address
DQ0-
DQ15
CE#
UB#/LB#
WE#
Read
Read
Write
Write


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