Electronic Components Datasheet Search |
|
TVP3409 Datasheet(PDF) 11 Page - Texas Instruments |
|
TVP3409 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 57 page 1–5 1.7 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION BLANK 7 I Blank (active low, TTL compatible). BLANK is latched on the rising edge of PCLK. When BLANK is low, the 1.44 mA current source on the analog outputs is turned off. The DACs ignore digital input from memory. In mode 14, pixel data is aligned with the rising edge of PCLK after BLANK rises. COMP 45 Compensation terminal. Bypass this terminal with an external 0.1 µF capacitor to VCC. D(7–0) 14 – 21 I/O Data bus (TTL compatible). Data is transferred between the data bus and the internal registers under control of the RD and WR signals. In a microprocessor unit (MPU) write operation, D(7–0) is latched on the rising edge of WR. To read data D(7–0) from the device, RD must be in an active low state. The rising edge of the RD signal indicates the end of a read cycle. Following the read cycle, the data bus goes to a high-impedance state. Note that for 6-bit operation, color data is contained in the lower six bits of the data bus. D0 is the LSB and D5 is the MSB. When the MPU writes color data, D6 and D7 are ignored. During MPU read cycles, D6 and D7 are a logic 0. FS(1,0) 2, 3 I Clock frequency select (TTL compatible). FS(1,0) select the register sets that determine the frequency of the clock synthesizers. FS(1,0) select the register sets when CC0(7) and CC0(3) = 0. When CC0(7) and CC0(3) = 1, bits in the CC register select the register sets. GND 10, 26, 36, 39, 44, 47, 60 Ground. GND terminals connect to circuit ground. OTCLKA 8 O Output clock A (TTL compatible). Output clock from analog PLLA synthesizer. OTCLKB 11 O Output clock B (TTL compatible). Output clock from analog PLLB synthesizer. PCLK 59 I Pixel clock (TTL compatible). The duty cycle can be 30% to 70%. The rising edge of the pixel clock latches the pixels and the BLANK input. P(12–13), P(14–15), P(0–7), P(8–11) 1,4, 12, 13, 51– 58, 64 – 67 I Pixel in (TTL compatible). These terminals are latched on the rising edge of PCLK. Pixels are presented to the DACs as color data in true-color modes and are used as addresses in the pseudocolor mode to look up color data in the color RAM. Unused inputs should be connected to GND. RD 5 I Read (active low, TTL compatible). When RD is low, data is transfered from the selected internal register to the data bus. RS(1,0) is latched on the falling edge of RD. RED, GREEN, BLUE 37, 38, 40 O Color analog out. High-impedance current sources that are capable of driving a double-terminated 75- Ω coaxial cable. REF 46 Voltage reference. REF should be bypassed with an external 0.1 µF capacitor to GND. RESET 62 I Reset (TTL compatible). This input resets internal registers to 0x00. RESET programs the clock synthesizer register sets to produce 28.322 MHz and 25.175 MHz. RSET 42 I Reference resistor. An external resistor (RSET) is connected between the RSET terminal and GND to control the magnitude of the full-scale current (refer to Section 2.6.8, DAC Gain for more information). RS(1,0) 23, 24 I Register select (TTL compatible). These inputs are sampled on the falling edge of RD or WR to determine which one of the internal registers is to be accessed. |
Similar Part No. - TVP3409_09 |
|
Similar Description - TVP3409_09 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |