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TVP3409 Datasheet(PDF) 46 Page - Texas Instruments |
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TVP3409 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 57 page  A–2 For the TVP3409, decouple VCC terminal to ground with a 0.1 F capacitor. For higher frequency pixel clocks (> 110 MHz) use a 0.01 µF capacitor in parallel with the 0.1 µF capacitor to shunt the higher frequency noise to ground. Power supply noise should be less than 200 mV for a good design. About 10% of any noise below 1 MHz is coupled onto the DAC outputs. As illustrated in Figure A–3, the COMP terminal should be decoupled with a 0.1 µF capacitor. For designs showing ghosting or smearing add a parallel COMP capacitance of 2.2 µF. Digital Signals The digital inputs should not travel over the analog power plane when possible. The RAMDAC should be located over the analog plane close to the digital-analog supply separation. The RAMDAC can also be placed over the supply separation so the digital pixel inputs are over the digital supply plane. The digital inputs, especially the P(15–0) high-speed inputs, should be isolated from the analog outputs. Placing the digital inputs over the digital supply reduces coupling into the analog supply plane. High-speed signals (both analog and digital) should not be routed under the RAMDAC. Avoid high slew-rate edges as they can contribute to undershoot, overshoot, ringing, EMI, and noise feed through. Edges can be slowed down using series termination (33 to 150 Ω). Edge noise can result when a digital signal propagates from an impedance mismatch while the signal rises. The reflection noise is particularly troublesome in the TTL threshold region. For a 2-ns edge, the trace length must be less than 4 inches. The clock signal trace should be as short as possible and should not run parallel to any high-speed signals. To ensure a quality clock signal without high frequency noise components, decouple the supply terminals on the clock driver. When necessary, transmission line techniques should be used on the clock by providing controlled impedance striplines and parallel termination. The 2x clock doubler in the TVP3409 helps to reduce signal quality problems and EMI radiations by reducing the frequency of the clock signal to the device. Analog Signals The load resistor should be as close as possible to the DAC outputs. The resistor should equal the destination termination which is usually a 75- Ω monitor. Unused analog outputs should be connected to ground. The DAC output traces should be as short as possible to minimize any impedance mismatch in the trace or video connector. Match the impedance of the R, G, B traces with the termination (75 Ω). The width of the traces are determined by the distance from the ground plane and the dielectric constant of the PC board material. Keep the R, G, B traces at least 20 to 50 mils wide. Series ferrite beads can be added to the analog video signal to reduce high frequency signals coupled onto the DAC outputs or reflected from the monitor. To reduce the interaction of the analog video return current with board components, a separate video ground return trace can be added to the ground plane or signal layer. This trace connects directly to the ground of the edge card connector (see Figure A–2). Using a separate video ground return path ensures that the RAMDAC ground is not corrupted with video return current. |
Similar Part No. - TVP3409_09 |
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Similar Description - TVP3409_09 |
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