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TVP3409 Datasheet(PDF) 30 Page - Texas Instruments |
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TVP3409 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 57 page  2–18 Table 2–19. Clock Synthesizer Reset Frequencies and FS(1,0) Terminal Logic Levels OTCLKA OTCLKB FS(1,0) CC(5,4) RESET FREQUENCY (MHz) FS(1,0) CC(1,0) RESET FREQUENCY (MHz) LL 00 25.057 LL 00 29.979 LH 01 28.189 LH 01 40.091 HL 10 50.114 HL 10 50.114 HH 11 75.170 HH 11 59.957 PCLK must meet the minimum high time as specified by the clock period and duty cycle AC specifications in Section 3, Electrical Characteristics. When switching PCLK frequencies, LUT corruption can occur if the PCLK high time is not met. Allow approximately one second after switching frequencies for the synthesizer outputs to settle to a valid clock signal. The diagram in Figure 2–5 is duplicated for the internal PLL (the TVP3409 has two PLLs on chip). XTAL OSC 1 ÷ (N + 2) Phase Compare Charge Pump Loop Filter VCO 1 ÷ (2P) 1 ÷ (M + 2) Clock Register Sets OTCLKA or OTCLKB XIN XOUT RESET Figure 2–4. Clock Synthesizer Block Diagram 2.6.4.1 Determining Output Frequency The output frequency, OTCLK, is determined by the following equation. OTCLK + F ref (M ) 2) (N ) 2) 2P (1) Where Fref is the input reference frequency, M is the feedback divider (8-bits), N is the input reference frequency divider (6-bits), and P is the postscaler divider or the exponent setting the output frequency divider (2-bits). Each synthesizer has four selectable frequencies. There are eight sets of M, N, and P registers. These registers are listed in Table 2–5. Clock synthesizer A (PLLA) and clock synthesizer B (PLLB) can be controlled by frequency select lines or control register bits. Each synthesizer is independently programmed to determine whether the FS(1,0) terminals or the control register bits control its frequency. When both synthesizers are programmed to use the frequency select lines, both synthesizers move in frequency at the same time to their respective register sets A, B, C, or D. When using the control register bits to control frequency, synthesizers A and B move in frequency independently and can move to different register sets. They do not have to both be set to the same register set A, B, C, or D. See Appendix A, Application Information for component connections and Appendix B, Register Summary for values for the clock synthesizer. 2.6.5 Clock Multiplier The clock multiplier is a third PLL that is automatically activated when either mode 2 or mode 14 is programmed. In mode 2, the multiplier doubles the PCLK. In mode 14, the PCLK is multiplied by 2/3. |
Similar Part No. - TVP3409_09 |
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Similar Description - TVP3409_09 |
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