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Integrated Silicon Solution, Inc. - www.issi.com

Rev. B

2/5/2015

IS42VS83200J / IS42VS16160J / IS42VS32800J

General Description

interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All

signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (VDD =

1.8V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic

column-address generation, the ability to interleave between internal banks to hide precharge time and the capability

to randomly change column addresses on each clock cycle during burst access.

A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE

function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles

and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented

starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The

registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command

in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the

bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with

address bits registered are used to select the starting column location for the burst access. Programmable READ or

WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

CLK

CKE

CS

RAS

CAS

WE

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA0

BA1

A10

A12

COMMAND

DECODER

&

CLOCK

GENERATOR

MODE

REGISTER

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

COLUMN

ADDRESS LATCH

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

DATA IN

BUFFER

DATA OUT

BUFFER

DQML

DQMH

DQ 0-15

13

13

9

13

13

9

16

16

16

16

512

(x 16)

8192

8192

8192

8192

MEMORY CELL

ARRAY

BANK 0

SENSE AMP I/O GATE

BANK CONTROL LOGIC

ROW

ADDRESS

BUFFER

A11

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