TUSB8020B

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SLLSEF6A – JULY 2014 – REVISED JULY 2014

7 Specifications

7.1 Absolute Maximum Ratings

(1)

over operating free-air temperature (unless otherwise noted)

MIN

MAX

UNIT

VDD

Steady-state supply voltage

–0.3

1.4

V

VDD33

Steady-state supply voltage

–0.3

3.8

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN

MAX

UNIT

Storage temperature range

–65

150

°C

–2000

2000

Electrostatic

V

discharge

–500

500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

1.1-V supply voltage

0.99

1.1

1.26

V

VDD33

3.3-V supply voltage

3

3.3

3.6

V

USB_VBUS

Voltage at USB_VBUS PAD

0

1.155

V

TUSB8020B

0

25

70

Operating free-air temperature range

°C

TUSB8020BI

–40

25

85

Operating junction temperature range

–40

25

105

°C

(1)

A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

TUSB8020B

PHP

UNIT

48 PINS

31.8

16.1

13

°C/W

0.5

12.9

0.9

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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