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TUSB7320 Datasheet(PDF) 5 Page - Texas Instruments

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Part # TUSB7320
Description  USB 3.0 xHCI Host Controller
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB7320 Datasheet(HTML) 5 Page - Texas Instruments

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TUSB7320, TUSB7340
www.ti.com
SLLSE76M – MARCH 2011 – REVISED JULY 2015
Clock and Reset Signals
PIN
I/O
DESCRIPTION
TUSB7320
TUSB7340
NAME
NO.
NO.
CLOCK AND RESET SIGNALS
Global power reset. This reset brings all of the TUSB73x0 internal registers to their default states.
I
When GRST# is asserted, the device is completely nonfunctional. GRST# should be asserted until all
GRST#
A15
A15
PU
power rails are valid at the device. If a 24 MHz or 48 MHz reference clock is used instead of a crystal,
GRST# must remain asserted until the 24 MHz or 48 MHz clock is stable.
Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be
XI
A23
A23
I
driven by the output of an external oscillator. When using a crystal a 2-M
Ω feedback resistor is
required between XI and XO.
Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an external
XO
A22
A22
O
oscillator this pin may be left unconnected. When using a crystal a 2-M
Ω feedback resistor is required
between XI and XO.
Frequency select. This terminal indicates the oscillator input frequency and is used to configure the
FREQSEL
B14
B14
I
correct PLL multiplier. This pin should be set low for normal operation.
PCIE_REFCLKP
A45
A45
I
PCI Express Reference Clock. PCIE_REFCLKP and PCIE_REFCLKN comprise the differential input
pair for the 100-MHz system reference clock.
PCIE_REFCLKN
B41
B41
I
PCI Express Reset Input. The PERST# signal is used to signal when the system power is stable. The
PERST#
A40
A40
I
PERST# signal is also used to generate an internal power on reset
PCI EXPRESS SIGNALS(1)
PCIE_TXP
B38
B38
O
PCI Express transmitter differential pair (positive).
PCIE_TXN
A41
A41
O
PCI Express transmitter differential pair (negative).
PCIE_RXP
B39
B39
I
PCI Express receiver differential pair (positive).
PCIE_RXN
A42
A42
I
PCI Express receiver differential pair (negative).
Wake. Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy’s
main power rails and reference clocks.
WAKE#
B35
B35
O
Note: WAKE# is not a failsafe I/O and should not be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
PCI Express REFCLK Request signal.
CLKREQ#
B36
B36
O
Note: CLKREQ# is not a failsafe I/O and should not be connected to a 3.3-V auxiliary supply while
VDD33 is not present.
USB DOWNSTREAM SIGNALS
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_DN1
A17
A17
O
Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX
differential pair.
USB_SSTXN_DN1
USB SuperSpeed transmitter differential pair (negative).
B15
B15
O
Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSTX
differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_DN1
A18
A18
I
Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX
differential pair.
USB SuperSpeed receiver differential pair (negative).
USB_SSRXN_DN1
B16
B16
I
Note: When routing, it is permissible to swap the positive and negative signals in Port 1 SSRX
differential pair.
USB_DP_DN1
A20
A20
I/O
USB High-speed differential transceiver (positive).
USB_DM_DN1
B18
B18
I/O
USB High-speed differential transceiver (negative).
USB DS Port 1 Power On Control for Downstream Power. The terminal is used for control of the
O
PWRON1#
B33
B33
downstream power switch. If the PWRON_POLARITY bit is set to 1, this pin is active high and the
PD
internal pulldown is disabled. This pin may be at low impedance when power rails are removed.
USB DS Port 1 Overcurrent Detection.
I
OVERCUR1#
A36
A36
0: overcurrent detected;
PU
1: overcurrent not detected
USB SuperSpeed transmitter differential pair (positive).
USB_SSTXP_DN2
A11
A11
O
Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSTX
differential pair.
USB SuperSpeed transmitter differential pair (negative).
USB_SSTXN_DN2
B10
B10
O
Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSTX
differential pair.
USB SuperSpeed receiver differential pair (positive).
USB_SSRXP_DN2
B9
B9
I
Note: When routing, it is permissible to swap the positive and negative signals in Port 2 SSRX
differential pair.
(1)
The only failsafe pins in the device are WAKE and CLKREQ#. No other pins are failsafe.
Copyright © 2011–2015, Texas Instruments Incorporated
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