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ADM1021A Datasheet(PDF) 4 Page - ON Semiconductor

Part No. ADM1021A
Description  Low Cost Microprocessor System Temperature Monitor Microcomputer
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADM1021A Datasheet(HTML) 4 Page - ON Semiconductor

 
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ADM1021A
http://onsemi.com
4
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(TA =TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted) (Note 1)
Parameter
Unit
Max
Typ
Min
Test Conditions/Comments
SMBus Interface (See Figure 2)
Logic Input High Voltage, VIH
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
2.2
V
Logic Input Low Voltage, VIL
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
0.8
V
SMBus Output Low Sink Current
SDATA Forced to 0.6 V
6.0
mA
ALERT Output Low Sink Current
ALERT Forced to 0.4 V
1.0
mA
Logic Input Current, IIH, IIL
−1.0
+1.0
mA
SMBus Input Capacitance, SCLK, SDATA
5.0
pF
SMBus Clock Frequency
100
kHz
SMBus Clock Low Time, tLOW
tLOW between 10% Points
4.7
ms
SMBus Clock High Time, tHIGH
tHIGH between 90% Points
4.0
ms
SMBus Start Condition Setup Time,
tSU:STA
4.7
ms
SMBus Repeat Start Condition
250
ns
Setup Time, tSU:STA
Between 90% and 90% Points
250
ns
SMBus Start Condition Hold Time, tHD:STA
Time from 10% of SDATA to 90% of SCLK
4.0
ms
SMBus Stop Condition Setup Time, tSU:STO
Time from 90% of SCLK to 10% of SDATA
4.0
ms
SMBus Data Valid to SCLK
Time for 10% or 90% of SDATA to 10% of SCLK
250
ns
Rising Edge Time, tSU:DAT
Time for 10% or 90% of SDATA to 10% of SCLK
250
ns
SMBus Data Hold Time, tBUF:DAT
0
ms
SMBus Bus Free Time, tBUF
Between Start/Stop Condition
4.7
ms
SCLK Falling Edge to SDATA
1
ms
Valid Time, tVD:DAT
Master Clocking in Data
1
ms
1. TMAX = 100C, TMIN = 0C
2. Operation at VDD = 5.0 V guaranteed by design; not production tested.
3. Guaranteed by design; not production tested.
Figure 2. Serial Bus Timing
STOP
START
tSU; DAT
tHIGH
tF
tHD; DAT
tR
tLOW
tSU; STO
STOP START
SCLK
SDATA
tBUF
tHD; STA
tHD; STA
tSU; STA


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