Philips Semiconductors

PHP/PHU101NQ03LT

TrenchMOS™ logic level FET

Product data

Rev. 02 — 25 February 2003

3 of 13

9397 750 10927

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Fig 1.

Normalized total power dissipation as a

function of mounting base temperature.

Fig 2.

Normalized continuous drain current as a

function of mounting base temperature.

Fig 3.

Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa16

0

40

80

120

0

50

100

150

200

Tmb (°C)

Pder

(%)

03ai19

0

40

80

120

0

50

100

150

200

Tmb (°C)

Ider

(%)

P

der

P

tot

P

tot 25 C

°

()

----------------------

100%

×

=

I

der

I

D

I

D25 C

°

()

-------------------

100%

×

=

03ai21

1

10

102

103

1

10

102

VDS (V)

ID

(A)

DC

100

µs

10 ms

Limit RDSon = VDS / ID

1 ms

tp = 10 µs