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PCA9555 Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCA9555 Datasheet(HTML) 5 Page - NXP Semiconductors |
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Philips Semiconductors Product data sheet PCA9555 16-bit I2C and SMBus I/O port with interrupt 2004 Sep 30 5 SIMPLIFIED SCHEMATIC OF I/Os WRITE PULSE DATA FROM SHIFT REGISTER VDD I/O PIN VSS WRITE CONFIGURATION PULSE D CK FF Q D CK Q FF D CK Q FF D CK Q FF INPUT PORT REGISTER POLARITY INVERSION REGISTER OUTPUT PORT REGISTER DATA FROM SHIFT REGISTER DATA FROM SHIFT REGISTER WRITE POLARITY PULSE CONFIGURATION REGISTER OUTPUT PORT REGISTER DATA INPUT PORT REGISTER DATA POLARITY REGISTER DATA READ PULSE SU01473 Q Q Q Q TO INT 100 k Ω Q1 Q2 NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/Os I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance path that exists between the pin and either VDD or VSS. |
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