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IS31FL3737 Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS31FL3737 Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
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9 / 28 page  IS31FL3737 Integrated Silicon Solution, Inc. – www.issi.com 9 Rev. A, 07/19/2016 DETAILED DESCRIPTION I2C INTERFACE The IS31FL3737 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3737 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Set A0 to “0” for a write command and set A0 to “1” for a read command. The value of bits A4:A1 are decided by the connection of the ADDR pin. The complete slave address is: Table 1 Slave Address: ADDR A7:A5 A4:A1 A0 GND 101 0000 0/1 SCL 0101 SDA 1010 VCC 1111 ADDR connected to GND, (A4:A1)= 0000; ADDR connected to VCC, (A4:A1)= 1111; ADDR connected to SCL, (A4:A1)= 0101; ADDR connected to SDA, (A4:A1)= 1010; The SCL line is uni-directional. The SDA line is bi- directional (open-collector) with a pull-up resistor (typically 1kΩ). The maximum clock frequency specified by the I2C standard is 1MHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3737. The timing diagram for the I2C is shown in Figure 4. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. After the last bit of the chip address is sent, the master checks for the IS31FL3737 ’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3737 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. Following acknowledge of IS31FL3737, the register address byte is sent, most significant bit first. IS31FL3737 must generate another acknowledge indicating that the register address has been received. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3737 must generate another acknowledge to indicate that the data was received. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. ADDRESS AUTO INCREMENT To write multiple bytes of data into IS31FL3737, load the address of the data register that the first data byte is intended for. During the IS31FL3737 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3737 will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS31FL3737 (Figure 7). READING OPERATION FEh, F1h and 18h~47h of page 0 can be read. To read the FEh and F1h, after IIC start condition, the bus master must send the IS31FL3737 device address with the R/ W ____ bit set to “0”, followed by the register address (FEh or F1h) which determines which register is accessed. Then restart I2C, the bus master should send the IS31FL3737 device address with the R/W ____ bit set to “1”. Data from the register defined by the command byte is then sent from the IS31FL3737 to the master (Figure 8). To read the 18h~47h of page 0, the FDh should write with 00h before follow the Figure 8 sequence to read the data, that means, when you want to read 18h~47h of page 0, the FDh should point to page 0 first and you can read the page 0 data. SDA SCL tHD,STA tLOW tHIGH tSU,DAT tHD,DAT tR tF tSU,STA tHD,STA tSU,STO tBUF S R P Start Condition Restart Condition Stop Condition Start Condition Figure 4 Interface timing |
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