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NT6880H Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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NT6880H Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 13 page  NT6880 4 2. System Reserved Registers Addr. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W $00C0 BT BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 W $00C1 TCON - - - - - - - ENBT W $00C2 CLRIRQX - - - - - - - CLRIRQTMR W $00C3 PORT0 PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 RW $00C4 PORT1 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 RW $00C5 PORT2 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 RW $00C6 PORT3 - - - PD34 PD33 PD32 PD31 PD30 RW $00C7 CLK - - - - - - - CLK RW $00C8 DATA - - - - - - - DATA RW $00C9 LED - - - - - LED2 LED1 LED0 W $00CA CLRWDT 0 1 0 1 0 1 0 1 W $00CB X X X X X X X X X X $00CC X X X X X X X X X X $00CD X X X X X X X X X X $00CE X X X X X X X X X X $00CF X X X X X X X X X X - : no effect X : access not allowed 3. ROM: 5K X 8 bits The built-in ROM program code, executed by the 6502 CPU, has a capacity of 5K X 8 bits and is addressed from EC00H to FFFFH. 4. SRAM: 160 X 8 bits The built-in SRAM is used for general purpose data memory and for the stack area. SRAM is addressed from 0000H to 009FH. User can allocate stack area in the SRAM by setting stack pointer register (S). Because the 6502 default stack pointer is 01FFH, it must be mapped to 009FH. Mapping from 01XX to 00XX is done internally by setting the S register to 9FH via software programming. For example : LDX #$9F TXS For compatibility to UM6868A with 128-byte SRAM, the user’s source code can not be changed. For example : LDX #$7F TXS 5. Power-On Reset Built-in power-on reset circuit can generate a 150ms pulse to reset the entire chip. The beginning of the 150ms pulse occurs at 60% of VDD when powered on. The start of 150ms pulse V DD t power 60% Figure 5.1. Power-On Reset Timing |
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