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MSC1200Y3 Datasheet(PDF) 45 Page - Texas Instruments |
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MSC1200Y3 Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 60 page  MSC1200 45 SBAS289E www.ti.com Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT Enable Wake Up Watchdog Timer. Wake up using watchdog timer interrupt. bit 2 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 Enable Wake Up External 1. Wake up using external interrupt source 1. bit 1 0 = Don’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 Enable Wake Up External 0. Wake up using external interrupt source 0. bit 0 0 = Don’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. System Clock Divider Register (SYSCLK) Enable Wake Up (EWU) Waking Up from IDLE Mode 7 6 5 4 3 2 1 0 Reset Value SFR C6H —— — — — EWUWDT EWUEX1 EWUEX0 00H 7 6 5 4 3 2 1 0 Reset Value SFR C7H 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00H DIVMOD DIVIDE MODE 00 Normal mode (default, no divide) 01 Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition or Normal mode write. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write. 11 Manual mode: start divide immediately; exit mode only on write to DIVMOD. DIVMOD DIVISION MODE STATUS 00 No divide 01 Divider is in Immediate mode 10 Divider is in Delay mode 11 Reserved DIV DIVISOR 000 Divide by 2 (default) fCLK = fSYS/2 001 Divide by 4 fCLK = fSYS/4 010 Divide by 8 fCLK = fSYS/8 011 Divide by 16 fCLK = fSYS/16 100 Divide by 32 fCLK = fSYS/32 101 Divide by 1024 fCLK = fSYS/1024 110 Divide by 2048 fCLK = fSYS/2048 111 Divide by 4096 fCLK = fSYS/4096 DIVMOD1-0 Clock Divide Mode bits 5-4 Write: Read: DIV2-0 Divide Mode bit 2-0 |
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