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MSC1200 Datasheet(PDF) 24 Page - Texas Instruments |
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MSC1200 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 60 page  MSC1200 24 SBAS289E www.ti.com CNTIF is generated and SCL is stretched by the MSC1200 until the I2CDATA register is written with a 0xFFH. The ACK/NACK from the master can then be read. Receive Once address recognition, R/W determination, and ACK/NACK are complete, I2CDATA must be written with 0xFFH to enable data reception. Upon completion of the data shift, the MSC1200 generates the CNT interrupt and stretches SCL. Received data can then be read from I2CDATA. After the serial data has been received, ACK/NACK is generated by writing 0x7FH (for ACK) or 0xFFH (for NACK) to I2CDATA. The write to I2CDATA clears the CNT interrupt and clock stretch. MEMORY MAP The MSC1200 contains on-chip SFR, Flash Memory, Scratchpad RAM Memory, and Boot ROM. The SFR regis- ters are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1200 are controlled through the SFR. Reading from undefined SFR will return zero; writing to undefined SFR registers is not recommended and may have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memories. The partition size is set through hardware configuration bits, which are programmed through serial programming. Both Program and Data Flash Memories are erasable and writable (programmable) in user application mode. However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be activated through the hardware configuration bits, which disables erase and writes to the first 4kB of Program Flash Memory or the entire Program Flash Memory in user application mode. FLASH MEMORY The MSC1200 uses a memory addressing scheme that separates Program Memory from Data Memory. The program and data segments can overlap since they are accessed by different instructions. Program Memory is fetched by the microcontroller automatically. There is one instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read lookup tables. The MSC1200 has three Hardware (HW) Configuration registers (HCR0, HCR1, and HCR2) that are programmable only during Flash Memory Programming mode. The MSC1200 allows the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1200Y3 contains 8kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Tables III and IV and Figure 18. The MSC1200 family offers two memory configurations. FIGURE 18. Memory Map. HCR0 MSC1200Y2 MSC1200Y3 DFSEL PM DM PM DM 00 0000-07FF 0400-0BFF 0000-0FFF 0400-13FF 01 0000-07FF 0400-0BFF 0000-17FF 0400-0BFF 10 0000-0BFF 0400-07FF 0000-1BFF 0400-07FF 11 (default) 0000-0FFF 0000 0000-1FFF 0000 TABLE IV. Flash Memory Partitioning Addresses. HCR0 MSC1200Y2 MSC1200Y3 DFSEL PM DM PM DM 00 2kB 2kB 4kB 4kB 01 2kB 2kB 6kB 2kB 10 3kB 1kB 7kB 1kB 11 (default) 4kB 0kB 8kB 0kB TABLE III. MSC1200Y Flash Partitioning. Unused Unused Unused 1K Internal Boot ROM 0000 H, 0k 2000 H, 8k (Y3) 1000 H, 4k (Y2) FC00 H F800 H FFFF H FFFF H On-Chip Flash Program Memory 0400 H, 1k 1400 H, 5k (Y3) 0C00 H, 3k (Y2) On-C hip Flash Data Memory |
Similar Part No. - MSC1200 |
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Similar Description - MSC1200 |
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