MSC1200 datasheet(54/60 Pages) TI

Part #	MSC1200

Description	Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory

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Manufacturer	TI [Texas Instruments]

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MSC1200

54

SBAS289E

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PSEN4-0

PSEN Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode.

bits 7-3

00000: General-Purpose I/O (default)

00001: SYSCLK

00011: Internal PSEN (refer to Figure 3 for timing)

00101: Internal ALE (refer to Figure 3 for timing)

00111: fOSC(buffered XIN oscillator clock)

01001: Memory WR (MOVX write)

01011: T0 Out (overflow)(1)

01101: T1 Out (overflow)(1)

01111: fMOD(2)

10001: SYSCLK/2 (toggles on rising edge)(2)

10011: Internal PSEN/2(2)

10101: Internal ALE/2(2)

10111: fOSC/2(2)

11001: Memory WR/2 (MOVX write)(2)

11011: T0 Out/2 (overflow)(2)

11101: T1 Out/2 (overflow)(2)

11111: fMOD/2(2)

NOTES: (1) On period of these signals equal to tCLK. (2) Duty cycle is 50%.

7

6

5

4

3

2

1

0

Reset Value

SFR F1H

PDICLK

PDIDAC

PDI2C

0

PDADC

PDWDT

PDSPI

6FH

Turning peripheral modules off puts the MSC1200 in the lowest power mode.

PDICLK

Internal Clock Control.

bit 7

0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode)

1 = Internal Oscillator and PLL Power Down (External Clock mode)

PDIDAC

IDAC Control.

bit 6

0 = IDAC On

1 = IDAC Power Down (default)

PDI2C

I2C Control.

bit 5

0 = I2C On (only when PDSPI = 1)

1 = I2C Power Down (default)

PDADC

ADC Control.

bit 3

0 = ADC On

1 = ADC, VREF, and Summation registers are powered down (default).

PDWDT

Watchdog Timer Control.

bit 2

0 = Watchdog Timer On

1 = Watchdog Timer Power Down (default)

PDST

System Timer Control.

bit 1

0 = System Timer On

1 = System Timer Power Down (default)

PDSPI

SPI Control.

bit 0

0 = SPI System On

1 = SPI System Power Down (default)

PSEN

/ALE Select (PASEL)

7

6

5

4

3

2

1

0

Reset Value

SFR F2H

PSEN4

PSEN3

PSEN2

PSEN1

PSEN0

0

00H

Power-Down Control Register (PDCON)

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