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MSC1200 Datasheet(PDF) 51 Page - Texas Instruments |
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MSC1200 Datasheet(HTML) 51 Page - Texas Instruments |
51 / 60 page MSC1200 51 SBAS289E www.ti.com SHF2-0 Shift Count. bits 2-0 SUMR0 Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. bits 7-0 Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register. Read: will clear the Summation Interrupt. Summation Register 1 (SUMR1) SHF2 SHF1 SHF0 SHIFT DIVIDE 00 0 1 2 00 1 2 4 01 0 3 8 01 1 4 16 10 0 5 32 10 1 6 64 1 1 0 7 128 1 1 1 8 256 7 6 5 4 3 2 1 0 Reset Value SFR E2H LSB 00H SUMR1 Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15. bits 7-0 Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 Reset Value SFR E3H 00H SUMR2 Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23. bits 7-0 7 6 5 4 3 2 1 0 Reset Value SFR E4H 00H SSCON1-0 Summation/Shift Control. bits 7-6 SCNT2-0 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the bits 5-3 SUMR0 register clears the interrupt. SCNT2 SCNT1 SCNT0 SUMMATION COUNT 00 0 2 00 1 4 01 0 8 01 1 16 10 0 32 10 1 64 1 1 0 128 1 1 1 256 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 DESCRIPTION 0 0 0 0 0 0 0 0 Clear Summation Register 0 0 0 1 0 0 0 0 CPU Summation on Write to SUMR0 0 0 1 0 0 0 0 0 CPU Subtraction on Write to SUMR0 1 0 x x x Note (1) Note (1) Note (1) CPU Shift Only 0 1 Note (1) Note (1) Note (1) x x x ADC Summation Only 1 1 Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation Completes then Shift Completes NOTES: (1) Refer to register bit definition. 7 6 5 4 3 2 1 0 Reset Value SFR E5H MSB 00H Summation Register 3 (SUMR3) SUMR3 Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31. bits 7-0 Summation Register 0 (SUMR0) |
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