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MSC1200 Datasheet(PDF) 41 Page - Texas Instruments |
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MSC1200 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 60 page  MSC1200 41 SBAS289E www.ti.com Interrupt Enable (IE) EA Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H). bit 7 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES0 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. bit 4 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H) or TI_0 (SCON0.1, SFR 98H) flags. ET1 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. bit 3 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H). EX1 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. bit 2 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. bit 1 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H). EX0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. bit 0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. Auxiliary Interrupt Status Register (AISTAT) 7 6 5 4 3 2 1 0 Reset Value SFR A7H SEC SUM ADC MSEC I2C CNT ALVD 0 00H SEC Second System Timer Interrupt Status Flag (lowest priority AI). bit 7 0: SEC Interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9H). SUM Summation Register Interrupt Status Flag. bit 6 0: SUM Interrupt cleared or masked. 1: SUM Interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2H). ADC ADC Interrupt Status Flag. bit 5 0: ADC Interrupt cleared or masked. 1: ADC Interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9H; if active, no new data will be written to the ADC Results registers). MSEC Millisecond System Timer Interrupt Status Flag. bit 4 0: MSEC Interrupt cleared or masked. 1: MSEC Interrupt active (it is cleared by reading MSINT, SFR FAH). I2C I2C Start/Stop Interrupt Status Flag. bit 3 0: I2C Start/stop Interrupt cleared or masked. 1: I2C Start/stop Interrupt active (it is cleared by writing to I2CDATA, SFR 9BH). CNT CNT Interrupt Status Flag. bit 2 0: CNT Interrupt cleared or masked. 1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9BH). ALVD Analog Low Voltage Detect Interrupt Status Flag. bit 1 0: ALVD Interrupt cleared or masked. 1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold). NOTE: If an interrupt is masked, the status can be read in AIPOL, SFR A4H. 7 6 5 4 3 2 1 0 Reset Value SFR A8H EA 0 0 ES0 ET1 EX1 ET0 EX0 00H |
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