NOIL2SM1300A-GWC datasheet(8/44 Pages) ONSEMI

Part #	NOIL2SM1300A-GWC

Description	High Speed CMOS Image Sensor

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NOIL2SM1300A

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8

SENSOR ARCHITECTURE

Image Sensor Core

The floor plan of the architecture is shown in Figure 5. The

sensor consists of a pixel array, analog front end, data block,

and LVDS transmitters and receivers. Separate modules for

the SPI, clock division, and sequencer are also integrated.

The image sensor of 1280 x 1024 active pixels is read out in

progressive scan.

This architecture enables programmable addressing in the

x-direction in steps of 24 pixels, and in the y-direction in

steps of one pixel. The starting point of the address can be

uploaded by the SPI.

The AFE prepares the signal for the digital data block

when the data is multiplexed and prepared for the LVDS

interface.

Figure 6. Floor Plan of the Sensor

Pixel Array

(1280x1024)

Analog Front End (AFE)

Data Formatting

LVDS Interface Tx and Rx

12 x LVDS Outputs at 630 Msps

28 Analog Channels, 31.5 Msps

12 x 10−bit Digital Channels, 63 Msps

Clock

Divider

24 x 10−bit Digital Channels, 31.5 Msps

31.5 Mhz

63 Mhz

315 Mhz

Clk X & Clk Y

Local registers

The 6T Pixel

To obtain the global shutter feature combined with a high

sensitivity and good parasitic light sensitivity (PLS),

implement the pixel architecture shown in Figure 6. This

pixel architecture is designed with a 14

mm x 14 mm pixel

pitch to meet the specifications listed in Table 1 and Table 2

on page 3. This architecture also enables pipelined or

triggered mode.

Figure 7. 6T Pixel Architecture

Vpix

Vmem

Reset

Sample

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NOIL2SM1300A-GWC Datasheet(PDF) 8 Page - ON Semiconductor

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