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TSB41BA3I Datasheet(PDF) 1 Page - Texas Instruments |
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TSB41BA3I Datasheet(HTML) 1 Page - Texas Instruments |
1 / 68 page TSB41BA3B IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS678 − SEPTEMBER 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Fully Supports Provisions of IEEE 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (B Signifies IEEE 1394b Signaling) D Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standards for High-Performance Serial Bus D Fully Interoperable With Firewire™, DTVLink, SB1394, DishWire, and i.LINK ™ Implementation of IEEE Std 1394 D Provides Three Fully Backward- Compatible, (1394a-2000 Fully Compliant) Bilingual 1394b Cable Ports at 400 Megabits per Second (Mbps) D Same Three Fully Backward-Compatible Ports Are 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbps D Full 1394a-2000 Support Includes: − Connection Debounce − Arbitrated Short Reset − Multispeed Concatenation − Arbitration Acceleration − Fly-By Concatenation − Port Disable/Suspend/Resume − Extended Resume Signaling for Compatibility With Legacy DV Devices D Power-Down Features to Conserve Energy in Battery-Powered Applications D Low-Power Automotive Sleep Mode Support D Fully Compliant With Open Host Controller Interface (OHCI) Requirements D Cable Power Presence Monitoring D Cable Ports Monitor Line Conditions for Active Connection to Remote Node D Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a-2000 Features D Interface to Link-Layer Controller Supports Low-Cost Texas Instruments Bus-Holder Isolation D Data Interface to Link-Layer Controller Terminal-Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (Eight Parallel Bits at 98.304 MHz) D Interoperable With Link-Layer Controllers Using 3.3-V Supplies D Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies D Low-Cost 49.152-MHz Crystal Provides Transmit and Receive Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz D Separate Bias (TPBIAS) for Each Port D Low-Cost, High-Performance 80-Terminal TQFP (PFP) Thermally Enhanced Package D Software Device Reset (SWR) D Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41BA3B Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane. D 1394a-2000-Compliant, Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Crosstalk Noise D Cable/Transceiver Hardware Speed and Port Mode Are Selectable by Terminal States D Supports Connection to CAT5 Cable Transceiver by Allowing Ports to be Forced to Beta-Only, 100-Mbps-Only D Supports Connection to S200 Plastic Optical Fiber Transceivers by Allowing Ports to be Forced to 1394b Beta-Only, S200-Mbps-Only, and S100-Mbps-Only D Optical Signal Detect Input for All Ports in Beta Mode Enables Connection to Optical Transceivers D Supports Use of 1394a Connectors by Allowing Ports 1 and 2 to Be Forced to 1394a-Only Mode Copyright © 2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. FireWire is a trademark of Apple Computer, Inc. MicroStar BGA and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. |
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