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TSB12LV22PZ Datasheet(PDF) 6 Page - Texas Instruments |
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TSB12LV22PZ Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 45 page  TSB12LV22 OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER SLLS290A − JULY 1998 − REVISED NOVEMBER 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCI Interface Control (Continued) PCI_PERR 49 I/O PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PAR when enabled through the command register. PCI_PME 17 O PCI power management extension. PCI_PME is an open-drain active-low signal, which, when asserted, indicates that a power management event has occurred. PCI_REQ 15 O PCI bus request. Asserted by the OHCI-Lynx to request access to the bus as an initiator. The host arbiter will assert the GNT signal when the OHCI-Lynx has been granted access to the bus. PCI_SERR 51 O PCI system error. Output pulsed from the OHCI-Lynx, when enabled, indicating an address parity error has occurred. The OHCI-Lynx needs not be the target of the PCI cycle to assert this signal. PCI_TRDY 45 I/O PCI target ready. TRDY indicates the PCI bus target’s ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted, until which wait states are inserted. IEEE1394 PHY/Link PHY_CTL1 PHY_CTL0 92 93 I/O Phy-link interface control. These bidirectional signals control passage of information between the two devices. The OHCI-Lynx can only drive these terminals after the PHY has granted permission following a link request (LREQ). PHY_DATA7 − PHY_DATA0 81,82, 84−86, 88−90 I/O Phy-link interface data. These bidirectional signals pass data between the OHCI-Lynx and the PHY device. These terminals are driven by the OHCI-Lynx on transmissions and are driven by the PHY on reception. Only DATA1−0 are valid for 100Mbit speeds, DATA4:0 are valid for 200Mbit speeds, and DATA7−0 are valid for 400 Mbit speeds. PHY_SCLK 95 I System clock. This input from the PHY provides a 49.152 MHz clock signal for data synchronization. PHY_LREQ 97 O Link request. This signal is driven by the OHCI-Lynx to initiate a request for the PHY to perform some service. Miscellaneous SDA 5 I/O Serial data. The OHCI-Lynx determines whether a two-wire serial ROM, or no serial ROM, is implemented at reset. If a two-wire serial ROM is detected, then this terminal provides the SDA serial data signaling. This terminal must be wired low to indicate no serial ROM is present. SCL 4 I/O Serial clock. The OHCI-Lynx determines whether a two-wire, or no serial ROM, is implemented at reset. If a two-wire serial ROM is implemented, then this terminal provides the SCL serial clock signaling. ISOLATED 79 I Phy−link iIsolation barrier mode. This terminal should be asserted when the PHY device is electrically isolated from the OHCI-Lynx. This input controls bus-hold I/Os. CYCLEIN 78 I Cycle input. This optional external 8 kHz clock input may be used as the cycle timer clock; it can also be used for synchronization with other system devices. CYCLEOUT 77 O Cycle output. This optional 8 kHz output may be used for cycle timer synchronization. GPIO3 3 I/O General-Purpose I/O [3] GPIO2 2 I/O General-Purpose I/O [2] LPS/GPIO1 99 I/O General-Purpose I/O [1]/ link power status output. Link power status indicates that link is powered and fully functional. BMC/LINKON/ GPIO0 98 I/O General-Purpose I/O [0]/bus manager contender output/LINKON#. LINKON. Receipt of a link-on packet. Once asserted LINKON remains asserted until LPS is asserted or the PHY register L bit is set to one TEST_EN 76 I Test enable. TEST_EN enables factory test mode when asserted. This terminal should be tied to VCC for normal operation. OHCI-Lynx controller programming model This section describes the internal registers used to program the OHCI-Lynx, including both PCI configuration registers and Open HCI registers. All registers are detailed in the same format. A brief description is provided for each register, followed by the register offset and a bit-table describing the reset state for each register. |
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