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IW1691-00 Datasheet(PDF) 7 Page - Dialog Semiconductor

Part # IW1691-00
Description  Digital PWM Current-Mode Controller for Quasi-Resonant Operation
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

IW1691-00 Datasheet(HTML) 7 Page - Dialog Semiconductor

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iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
Rev. 2.0
iW1691
Page 7
FebRuaRy 3, 2012
9.1 Pin Detail
Pin 2 – V
SENSE
Sense signal input from auxiliary winding. This provides the
secondary voltage feedback used for output regulation.
Pin 3 – V
iN
Sense signal input from the rectified line voltage. V
IN is used
for line regulation. The input line voltage is scaled down
using a resistor network. It is used for input undervoltage
and overvoltage protection. This pin also provides the supply
current to the IC during start-up.
Pin 4 – SD
External shutdown control. If the shutdown control is not
used, this pin should be connected to GND via a resistor.
(see Section 10.16).
Pin 5 – GND
Ground.
Pin 6 – i
SENSE
Primary current sense. Used for cycle by cycle peak current
control.
Pin 7 – OUTPUT
Gate drive for the external MOSFET switch.
Pin 8 – V
CC
Power supply for the controller during normal operation. The
controller will start up when V
CC reaches 12 V (typical) and
will shut-down when the V
CC voltage is below 6 V (typical). A
decoupling capacitor should be connected between the V
CC
pin and GND.
9.2 Start-up
Prior to start-up the V
IN pin charges up the VCC capacitor
through the diode between V
IN and VCC (see Figure 8.1).
When V
CC is fully charged to a voltage higher than the start-
up threshold V
CC(ST), the ENABLE signal becomes active and
enables the control logic; the V
IN switch turns on, and the
analog-to-digital converter begins to sense the input voltage.
Once the voltage on the V
IN pin is above VINSTLOW , the iW1691
commences soft start function. An adaptive soft-start control
algorithm is applied at startup state, during which the initial
output pulses will be small and gradually get larger until the
full pulse width is achieved. The peak current is limited cycle
by cycle by Ipeak comparator.
If at any time the V
CC voltage drops below VCC(UVL) threshold
then all the digital logic is reset. At this time V
IN switch turns
off so that the V
CC capacitor can be charged up again towards
the start-up threshold.
VCC
VCC(ST)
ENABLE
Start-up
Sequencing
VIN
Figure 9.1 : Start-up Sequencing Diagram
9.3 Understanding Primary Feedback
Figure 9.2 illustrates a simplified flyback converter. When the
switch Q1 conducts during t
ON(t), the current ig(t) is directly
drawn from rectified sinusoid v
g(t). The energy Eg(t) is stored
in the magnetizing inductance L
M. The rectifying diode D1 is
reverse biased and the load current I
O is supplied by the
secondary capacitor C
O. When Q1 turns off, D1 conducts
and the stored energy E
g(t) is delivered to the output.
+
vin(t)
TS(t)
IO
VO
VAUX
N:1
D1
Q1
VAUX
CO
vg(t)
ig(t)
+
iin(t)
id(t)
Figure 9.2 : Simplified Flyback Converter
In order to tightly regulate the output voltage, the information
about the output voltage and load current needs to be
accurately sensed. In the DCM flyback converter, this
information can be read via the auxiliary winding. During the
Q
1 on-time, the load current is supplied from the output filter
capacitor C
O. The voltage across LM is vg(t), assuming the
voltage dropped across Q
1 is zero. The current in Q1 ramps
up linearly at a rate of:
()
()
g
g
M
di t
v t
dt
L
=
(9.1)
At the end of on-time, the current has ramped up to:


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