ISP1583 datasheet(17/87 Pages) PHILIPS

Part #	ISP1583

Description	Hi-Speed Universal Serial Bus peripheral controller

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Product data

Rev. 03 — 12 July 2004

17 of 87

9397 750 13461

pin INT; see Table 22. Default settings after reset are active LOW and level mode.

When pulse mode is selected, a pulse of 60 ns is generated when the OR-ed

combination of all interrupt bits changes from logic 0 to logic 1.

Figure 4 shows the relationship between the interrupt events and pin INT.

Each of the indicated USB and DMA events is logged in a status bit of the Interrupt

register and the DMA Interrupt Reason register, respectively. Corresponding bits in

the Interrupt Enable register and the DMA Interrupt Enable register determine

whether or not an event will generate an interrupt.

Interrupts can be masked globally by means of bit GLINTENA of the Mode register.

Field CDBGMOD[1:0] of the Interrupt Conﬁguration register controls the generation

of the INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt

Conﬁguration register controls the generation of the INT signals for the IN pipe. Field

DDBGMODOUT[1:0] of the Interrupt Conﬁguration register controls the generation of

the INT signals for the OUT pipe; see Table 26.

8.12.2

Interrupt control

Bit GLINTENA in the Mode register is a global enable/disable bit. The behavior of this

bit is given in Figure 5.

Event A: When an interrupt event occurs (for example, SOF interrupt) with

bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will,

however, be registered in the corresponding Interrupt register bit.

Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in

the Interrupt register is already set.

Event C: If the ﬁrmware sets bit GLINTENA to logic 0, pin INT will still be asserted.

The bold dashed line shows the desired behavior of pin INT.

Deassertion of pin INT can be achieved either by clearing all the Interrupt register or

the DMA Interrupt Reason register, depending on the event.

Remark: When clearing an interrupt event, perform write to all the bytes of the

register.

For more information on interrupt control, see Section 9.2.2, Section 9.2.5 and

Section 9.5.1.

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