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ISP1583 Datasheet(PDF) 8 Page - NXP Semiconductors |
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ISP1583 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 87 page Philips Semiconductors ISP1583 Hi-Speed USB peripheral controller Product data Rev. 03 — 12 July 2004 8 of 87 9397 750 13461 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. READY/ IORDY 15 I/O Signal ready output — Used in generic processor mode: • LOW: the ISP1583 is processing a previous command or data and is not ready for the next command or data transfer • HIGH: the ISP1583 is ready for the next microprocessor read or write. DMA ready input — Used in split bus mode for accessing ATA/ATAPI peripherals (PIO mode only). bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant[6] INT 16 O interrupt output; programmable polarity (active HIGH or LOW) and signaling (edge or level triggered) CMOS output; 8 mA drive DA2[5] 17 O address output to select the Task File register of an ATA/ATAPI device; see Table 59 CMOS output; 8 mA drive CS_N 18 I chip selection input input pad; TTL; 5 V tolerant[6] RW_N/ RD_N 19 I Read and write input — For Motorola style, this function is determined by pin MODE0 = LOW during power-up. Read input — For 8051 style, this function is determined by pin MODE0 = HIGH during power-up. input pad; TTL; 5 V tolerant[6] DS_N/ WR_N 20 I Data selection input — For Motorola style, this function is determined by pin MODE0 = LOW at power-up. Write input — For 8051 style, this function is determined by pin MODE0 = HIGH at power-up. input pad; TTL; 5 V tolerant[6] CS0_N[5] 21 O chip selection output 0 for ATA/ATAPI device; see Table 59 CMOS output; 8 mA drive CS1_N[5] 22 O chip selection output 1 for ATA/ATAPI device; see Table 59 CMOS output; 8 mA drive AD0 23 I/O bit 0 of multiplexed address and data bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] AD1 24 I/O bit 1 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] AD2 25 I/O bit 2 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] VCC(I/O)[3] 26 - I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.15 AD3 27 I/O bit 3 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] AD4 28 I/O bit 4 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] AD5 29 I/O bit 5 of multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant[6] Table 2: Pin description…continued Symbol[1] Pin Type[2] Description |
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