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ISP1583 Datasheet(PDF) 67 Page - NXP Semiconductors |
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ISP1583 Datasheet(HTML) 67 Page - NXP Semiconductors |
67 / 87 page Philips Semiconductors ISP1583 Hi-Speed USB peripheral controller Product data Rev. 03 — 12 July 2004 67 of 87 9397 750 13461 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 13.1 Register access timing 13.1.1 Generic processor mode BUS_CONF = H: generic processor mode: • MODE0 = H: 8051 style; see Figure 20 • MODE0 = L: Motorola style; see Figure 21. TPERIOD is the bit duration corresponding with the USB data rate. Fig 18. Receiver differential data jitter. mgr871 TPERIOD tJR differential data lines +3.3 V 0 V tJR1 tJR2 consecutive transitions N × TPERIOD + tJR1 paired transitions N × TPERIOD + tJR2 Fig 19. Receiver SE0 width tolerance. mgr872 differential data lines +3.3 V 0 V tFST VIH(min) Table 101: ISP1583 register access timing parameters: separate address and data buses VCC(I/O) = 3.3 V; VCC(3V3) = 3.3 V; VGND =0V; Tamb = −40 °Cto+85 °C. Symbol Parameter Min Max Unit Reading tRLRH RD_N LOW pulse width >tRLDV -ns tAVRL address set-up time before RD_N LOW 0 - ns tRHAX address hold time after RD_N HIGH 0 - ns tRLDV RD_N LOW to data valid delay - 26 ns tRHDZ RD_N HIGH to data outputs 3-state delay 0 15 ns tRHSH RD_N HIGH to CS_N HIGH delay 0 - ns tSLRL CS_N LOW to RD_N LOW delay 2 - ns |
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